D_T_JK_constraints - 8th NASA Symposium on VLSI Design,...

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8 th NASA Symposium on VLSI Design, Albuquerque, NM, Oct 20-21, 1999. D, T and JK Constraints in Asynchronous Synthesis David F. Cox Research Professor dcox@mrc.unm.edu (505) 272-7045 NASA Institute of Advanced Microelectronics Microelectronics Research Center University of New Mexico 801 University Blvd. SE, Suite 206 Albuquerque, New Mexico 87106 Abstract - Low power and high speed are considered benefits in space electronics. Asynchronous circuits can provide both low power and higher speed operation in electronic circuits. Techniques are given that allow designing asynchronous circuits with the state variables being assigned to flip-flops. It is shown that any asynchronous circuit may be designed using RS flip-flops whereas D, T, and JK flip-flops may be used if certain state entry conditions are met. 1 Introduction Asynchronous design was given a formal methodology by David Huffman in 1954 [1]. This paper will discuss extending his techniques to designs using flip-flops as the feedback elements instead of combinatorial circuits. An example design is described to provide the basis for a state diagram from which the hardware designs will be derived. 2 Example An example design of a simple counter will be used to illustrate the techniques. The counter will count to three, have an output on the third count and then reset to begin the count. The timing diagram is given in Figure 1. Asynchronous circuits can be described, and states assigned by using timing diagrams, state diagrams or transition tables [2], [3]. This example will use a timing diagram. It should be noted that any state diagram can be used as long as it represents a legitimate sequential system. The input to this example is labeled “in” and the output is labeled “out”. The output is seen to commence with the falling of the second input pulse but could also have been simply coincident with the third input pulse.
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8 th NASA Symposium on VLSI Design, Albuquerque, NM, Oct 20-21, 1999. in: (state) 1 2 3 4 5 6 1 2 out: Figure 1 . Timing Diagram for Counter. The flow table and final Karnaugh map can be generated from the timing diagram as shown in Figure 2. The circled entries are stable states. i n i n state 0 1 out q1q2q3 0 1 out 1 1 2 0 (1) 000 000 001 0 2 3 2 0 (2) 001 011 001 0 3 3 4 0 (3) 011 011 010 0 4 5 4 0 (4) 010 110 010 0 5 5 6 1 (6) 100 000 100 1 6 1 6 1 101 - - - 111 - - - (5) 110 110 100 1 Figure 2. Flow Table and Karnaugh Map for Counter. The states q1, q2 and q3 are then separated out into individual maps and combinatorial expressions are then generated for each of them. Each combinatorial expression will typically have feedback from the state variables. 3 RS Characteristic Equation An implementation of the counter (or any asynchronous circuit) can be done using RS flip-flops in the following manner.
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This note was uploaded on 12/15/2010 for the course ECE 271 taught by Professor Garrisongreenwood during the Spring '10 term at Pohang University of Science and Technology.

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D_T_JK_constraints - 8th NASA Symposium on VLSI Design,...

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