CA HW3 - Step 1 At first, I remained the original...

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Step 1 At first, I remained the original configuration for this problem and simulated. IL1Size = 8*1024 IL1CacheLine = 32 IL1Associativity = 1 DL1Size = 8*1024 DL1CacheLine = 32 DL1Associativity = 1 L2Size = 64*1024 L2CacheLine = 64 L2Associativity = 1 NumIntegerALU = 4 NumIntegerMULT = 1 NumMemPort = 1 ClockFrequency = 100000000 [BPredIssueX] type = "nottaken" size = 2048 bits = 2 Simulation result: Exe Speed Exe MHz Exe Time Sim Time (100MHz) 768.648 KIPS 1.7879 MHz 1150.710 secs 20573.374 msec Proc Avg.Time BPType Total RAS BPred BTB BTAC 0 31.215 nottaken 52.27% ( 98.73% of 6.82%) 48.86% ( 0.00% of 0.00%) 0.00% nInst BJ Load Store INT FP : LD Forward , Replay : Worst Unit (clk) 0 884491022 13.44% 20.60% 6.60% 59.37% 0.00% : 5.26% 432 inst/repl : ALUIssueX 0.91 Proc IPC CPI Cycles Busy LDQ STQ IWin ROB Regs Ports TLB maxBr MisBr Br4Clk Other 0 0.430 2.326 2057337416 10.7 0.0 0.0 0.7 0.0 0.0 0.0 0.0 0.0 88.4 0.0 0.1 ################################################################ ################
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From the result we can see that ALUIssuex is the Worst Unit during the simulation. Thus to improve the performance, we need to increase the number of ALUs. Step 2 One way to improve the performance of ALU is increasing the number of ALU. To test how good this change would be,I first increase it from 1 to 2. But ALU is still the worst unit, so I continued to increase its quantity to 4. And this time none is the worst unit. Simulation result: Exe Speed Exe MHz Exe Time Sim Time (100MHz) 681.479 KIPS 1.5251 MHz 1297.900 secs 19794.520 msec Proc Avg.Time BPType Total RAS BPred BTB BTAC 0 29.850 nottaken 52.27% ( 98.73% of 6.82%) 48.86% ( 0.00% of 0.00%) 0.00% nInst BJ Load Store INT FP : LD Forward , Replay : Worst Unit (clk) 0 884491022 13.44% 20.60% 6.60% 59.37% 0.00% : 5.27% 434 inst/repl : 0.00 Proc IPC CPI Cycles Busy LDQ STQ IWin ROB Regs Ports TLB maxBr MisBr Br4Clk Other 0 0.447 2.238 1979452044 11.2 0.0 0.0 0.6 0.0 0.0 0.0 0.0 0.0 88.1 0.0 0.1 ################################################################ ################ Simulation result (# of ALU = 4) This time, the worst unit is none and the Sim Time decreased to 19794.520 msec Step 3 From the percentage row we can see that misbranch caused the majority of stalls. So we should change the branch prediction model. At first, I tried the 2048bits, 2-bits dynamic branch predictor. Exe Speed Exe MHz Exe Time Sim Time (100MHz) 683.036 KIPS 1.144 MHz 1294.940 secs 14948.794 msec Proc Avg.Time BPType Total RAS BPred BTB BTAC 0 44.710 nottaken 77.87% ( 98.73% of 6.82%) 76.35% ( 93.20% of 37.74%) 0.00% nInst BJ Load Store INT FP : LD Forward , Replay : Worst Unit (clk) 0 884491022 13.44% 20.60% 6.60% 59.37% 0.00% : 7.65% 343
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inst/repl : 0.00 Proc IPC CPI Cycles Busy LDQ STQ IWin ROB Regs Ports TLB maxBr MisBr Br4Clk Other 0 0.593 1.685 1490473444 14.8 0.0 0.0 2.6 0.1 0.0 0.0 0.0 0.0 81.1 0.0 1.3 ################################################################ ################ With this change, the SimTime is decreased a lot, which means misbranch take a
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This note was uploaded on 12/17/2010 for the course CE 4824 taught by Professor Luca during the Fall '10 term at Columbia.

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CA HW3 - Step 1 At first, I remained the original...

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