AppendixA_Pipelining - Computer Architecture Appendix A...

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Unformatted text preview: Computer Architecture Appendix A Pipelining Prof. Jerry Breecher CSCI 240 Fall 2003 Appendix A - Pipelining 2 Introduction This material was previously, in the second edition of Hennessey & Patterson, written as Chapter 3. In their view this has become strictly undergraduate material and has been put into Appendix A. All of this we should have seen in CS140. So were going to treat it as review and spend only a limited time on it. Appendix A - Pipelining 3 Introduction A.1 What is Pipelining? A.2 The Major Hurdle of Pipelining-Structural Hazards Data Hazards Control Hazards A.3 How is Pipelining Implemented A.4 What Makes Pipelining Hard to Implement? A.5 Extending the MIPS Pipeline to Handle Multi-cycle Operations Appendix A - Pipelining 4 What Is Pipelining Laundry Example Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes Dryer takes 40 minutes Folder takes 20 minutes A B C D Appendix A - Pipelining 5 What Is Pipelining Sequential laundry takes 6 hours for 4 loads If they learned pipelining, how long would laundry take? A B C D 30 40 20 30 40 20 30 40 20 30 40 20 6 PM 7 8 9 10 11 Midnight T a s k O r d e r Time Appendix A - Pipelining 6 What Is Pipelining Start work ASAP Pipelined laundry takes 3.5 hours for 4 loads A B C D 6 PM 7 8 9 10 11 Midnight T a s k O r d e r Time 30 40 40 40 40 20 Appendix A - Pipelining 7 Pipelining Lessons Pipelining doesnt help latency of single task, it helps throughput of entire workload Pipeline rate limited by slowest pipeline stage Multiple tasks operating simultaneously Potential speedup = Number pipe stages Unbalanced lengths of pipe stages reduces speedup Time to fill pipeline and time to drain it reduces speedup A B C D 6 PM 7 8 9 T a s k O r d e r Time 30 40 40 40 40 20 What Is Pipelining Appendix A - Pipelining 8 MIPS Without Pipelining What Is Pipelining Memory Access Write Back Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc IR L M D Appendix A - Pipelining 9 MIPS Functions What Is Pipelining Memory Access Write Back Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc IR L M D Instruction Fetch (IF): Send out the PC and fetch the instruction from memory into the instruction register (IR); increment the PC by 4 to address the next sequential instruction. IR holds the instruction that will be used in the next stage. NPC holds the value of the next PC. Passed To Next Stage IR <- Mem[PC] NPC <- PC + 4 Appendix A - Pipelining 10 MIPS Functions What Is Pipelining Memory Access Write Back Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc IR L M D Instruction Decode/Register Fetch Cycle (ID): Decode the instruction and access the register file to read the registers....
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This note was uploaded on 12/17/2010 for the course CSCI 240 taught by Professor Nguyenkimkhanh during the Spring '10 term at Technische Universiteit Eindhoven.

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AppendixA_Pipelining - Computer Architecture Appendix A...

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