Chap7-logical-shift-1

# Chap7-logical-shift-1 - Overview Bitwise Logical Operations...

This preview shows pages 1–5. Sign up to view the full content.

Overview ° Bitwise Logical Operations OR AND XOR ° Shift Operations Shift Left Shift Right Rotate Field Extraction Review: Assembly Variables: Registers ° Assembly Language uses registers as operands for data processing instructions r0 r1 r2 r3 r r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 Register No. a1 a2 a3 a4 v1 v2 v3 v4 v5 v6 v7 v8 ip sp lr pc Register Name All register are identical in hardware, except for PC PC is the program Counter; It always contains the address the instruction being fetched from memory By Software convention we use different registers for different things C Function Variables: v1 v7 Scratch Variables: a1 a4

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Bitwise Operations (#1/2) ° Up until now, we ʼ ve done arithmetic ( add , sub, rsb ) and data movement mov . ° All of these instructions view contents of register as a single quantity (such as a signed or unsigned integer) ° New Perspective : View contents of register as 32 bits rather than as a single 32-bit number Bitwise Operations (#2/2) ° Since registers are composed of 32 bits, we may want to access individual bits rather than the whole. ° Introduce two new classes of instructions/Operations: Logical Instructions Shift Operators
Logical Operations ° Operations on less than full words Fields of bits or individual bits ° Think of word as 32 bits vs. 2 ʼ s comp. integers or unsigned integers ° Need to extract bits from a word, or insert bits into a word ° Extracting via Shift instructions C operators: << (shift left), >> (shift right) ° Inserting and inverting via And/OR/EOR instructions C operators: (bitwise AND), | (bitwise OR), ^ (bitwise EOR) Logical Operators ° Operator Names: and , bic, orr, eor : ° Operands: Destination : Register Operand #1: Register Operand #2: Register, or Shifted registers, or an immediate Example: and a1, v1, v2 and a1, v1, v2, lsl #5 and a1, v1, v2, lsl v3 and a1, v1, #0x40 ° ARM Logical Operators are all bitwise , meaning that bit 0 of the output is produced by the respective bit 0 ʼ s of the inputs, bit 1 by the bit 1 ʼ s, etc.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Logical AND Operator (#1/3) ° AND:Note that and ing a bit with 0 produces a 0 at the output while and ing a bit with 1 produces the original bit. ° This can be used to create a
This is the end of the preview. Sign up to access the rest of the document.

## This note was uploaded on 12/20/2010 for the course CSC CSCC85 taught by Professor Lorincz during the Spring '10 term at University of Toronto- Toronto.

### Page1 / 14

Chap7-logical-shift-1 - Overview Bitwise Logical Operations...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online