Chap7-logical-shift-2

# Chap7-logical-shift-2 - Overview ° Shift Operations •...

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Unformatted text preview: Overview ° Shift Operations • Field Insertion ° Multiplication Operations • Multiplication • Long Multiplication • Multiplication and accumulation • Signed and unsigned multiplications Review: ARM Instructions So far add sub mov and bic orr eor Data Processing Instructions with shift and rotate lsl, lsr, asr, ror Review: Masking via Logical AND ° AND:Note that and ing a bit with 0 produces a 0 at the output while and ing a bit with 1 produces the original bit. ° This can be used to create a mask . • Example: 1011 0110 1010 0100 0011 1101 1001 1010 0000 0000 0000 0000 0000 0000 1111 1111 • The result of and ing these two is: 0000 0000 0000 0000 0000 0000 1001 1010 Mask: Review: Masking via Logical BIC ° BIC (AND NOT):Note that bic ing a bit with 1 produces a 0 at the output while bic ing a bit with 0 produces the original bit. ° This can be used to create a mask . • Example: 1011 0110 1010 0100 0011 1101 1001 1010 0000 0000 0000 0000 0000 0000 1111 1111 • The result of bic ing these two is: 1011 0110 1010 0100 0011 1101 0000 0000 Mask: Extracting a feld oF bits (#1/2) ° ShiFt feld as Far leFt as possible (9 31) and then as Far right as possible (31 7) ° Extract bit feld From bit 9 (leFt bit no.) to bit 2 (size=8 bits) oF register v1, place in rightmost part oF register a1 1 2 3 4 5 6 7 8 9 31 v1 0000 0000 0000000000000000 a1 00 0000 0000000000000000 a1 0000 0000 0000000000000000 a1 v1 Extracting a feld oF bits (#2/2) mov a1, v1, lsl #22 ;8 bits to left end (31-9) 00 0000 0000000000000000 a1 v1 mov a1, a1, lsr #24 ;8 bits to right end(7-0) 00 0000 0000000000000000 a1 0000 0000 0000000000000000 a1 Inserting a feld oF bits ° ShiFt leFt feld 2 bits, Mask out feld, OR in feld ° Insert bit feld into bit 9 (leFt bit no.) to bit 2 (size=8 bits) oF register a1 From rightmost part oF register v1 (rest is 0) ° mov a2, v1, lsl #2 ; field left 2 bic a1, a1, #0x3FC ; mask out 9-2 ; 0x03FC = 0011 1111 1100 orr a1, a1, a2 ; OR in field 1 2 3 4 5 6 7 8 9 31 0000 0000 0000000000000000 v1 a1 00000000 a1 masked 0000 00 00 0000000000000000 a2=v1<<2 a1 ored a2 ; bic stands For ʻ bit clear, where ʻ 1 ʼ in the second operand clears ; the corresponding bit in the frst...
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## This note was uploaded on 12/20/2010 for the course CSC CSCC85 taught by Professor Lorincz during the Spring '10 term at University of Toronto.

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Chap7-logical-shift-2 - Overview ° Shift Operations •...

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