EECS 215 F07 Problem Set 7 solutions

EECS 215 F07 Problem Set 7 solutions - so putting an...

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bc fj,, e7y;dU~f [e8~flle Seed b7 dH fiLhf go hef// 4 /v +.st 5odfCd L, IV i, --b 4 / Do KVL arovl d . * .L,= L t YO (a5 i,) c \o;,=o 50 - /(CL 9, onfw node y5 i, z o.si, 50 i &) - vi3 - 1 1- rL. 30 r130s a-c L' - I
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Yo- - /&3(;~~-6)& dl
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GI3 qPN" 1% TIP d
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8) (first part) There are a few ways to do this in PSpice. I simulated the circuit with a 20 A input in the bias point simulation to figure out what v c (t) would be at t = 0. Then I used this as an initial condition on the capacitor and did the time domain analysis. Be careful with your pin orientation on the capacitors. There is no clearly marked “+” or “-“ pin,
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Unformatted text preview: so putting an initial condition on a capacitor which is upside down even though you dont even know it, could happen. Above: Schematic for question 8, part 1. Above: Current through capacitor, part 1 Above: Voltage Across Capacitor, part 1 Above: Current through source, part 1 8.) Second Part. Use the same schematic as shown earlier. Except replace IPULSE with IPWL. For IPWL, I have I1 =-20, I2 = -32, I3 = 0, at T1 = 0, T2 = 20, T3 = 60. Above: Current Through capacitor Above: Current Across Capacitor (Part 2) Above: Current through source(note that it is negative because of my orientation of the current supply.)...
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This note was uploaded on 12/20/2010 for the course EECS 215 taught by Professor Phillips during the Fall '08 term at University of Michigan.

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EECS 215 F07 Problem Set 7 solutions - so putting an...

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