ps1sol_ee550_fall08

# ps1sol_ee550_fall08 - UNIVERSITY OF SOUTHERN CALIFORNIA...

This preview shows pages 1–3. Sign up to view the full content.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: UNIVERSITY OF SOUTHERN CALIFORNIA, FALL 2008 1 EE 550: Problem Set # 1 Solution I. LINK UTILIZATION a) From Fig. 1.5 in the textbook, since ∑ N ( t ) i =1 X i is the time spent transmitting during [0 ,t ] , ∑ N ( t ) i =1 X i ≤ t . b) N ( t ) X i =1 X i ≤ t ⇒ N ( t ) t 1 N ( t ) N ( t ) X i =1 X i ≤ 1 . (1) Let t → ∞ , we have N ( t ) t → λ and 1 N ( t ) ∑ N ( t ) i =1 X i → X . Thus (1) yields λ X ≤ 1 . c) ρ = λ X is the total workload arriving per unit time. So intuitively it is the fraction of time that the link is busy. Actually, from part (a) (b) we have lim t →∞ time busy during [0 ,t ] t = lim t →∞ 1 t N ( t ) X i =1 X i = λ X = ρ. II. VIRTUAL CIRCUIT VERSUS DATAGRAM a) In VC mode, each packet takes 8 · 8 + 512 64 · 10 3 = 9 ms to go through one link. To transmit N packets over 6 links, it requires 300 ms as setup time, 9 · 6 = 54 ms to transmit the first packet to the destination, and 9( N- 1) ms to transmit the rest N- 1 packets to the destination. The total required time is 300 + 54 + 9( N- 1) = 9N + 345 ms. b) In Datagram mode, each packet requires 16 · 8 + 512 64 · 10 3 = 10 ms to go through one link. Similar as in VC mode (except that datagram mode needs no setup time), the total time required to transmit N packets is 10 · 6 + 10( N- 1) = 10N + 50 ms. c) We use datagram mode when 9 N + 345 > 10 N + 50 , i.e., N < 295 . III. ERROR DETECTION BLOCK CODES p4 d1 p1 d4 d2 p3 d3 p2 1 1 1 1 Fig. 1. A ring code for the special case k = 4 , together with an example codeword for the date string { d 1 ,d 2 ,d 3 ,d 4 } = { 0110 } . (a) If a data bit is in error. Its two neighboring parity bits will indicate the error by computing modulo- 2 sums. Likewise, if a parity check bit is in error, it will fail the modulo- 2 sum test. Thus the code can detect single bit errors. The above observations also show that the code can correct single bit errors: When there are two neighboring parity bits that both indicate an error, we know the data bit in between needs to be corrected. When there is only one parity bit indicating an error, it is the one to be corrected. (b) There are three cases to consider: If two data bits are in error, or one data bit and one parity bit are in error, we can always identify a sequence of three bits in the received bit string of the form data-parity-data with only one error data bit and two correct bits. The parity bit in the UNIVERSITY OF SOUTHERN CALIFORNIA, FALL 2008 2 3-bit sequence will indicate the error. If two parity check bits are in error, likewise, we can find a-bit sequence will indicate the error....
View Full Document

{[ snackBarMessage ]}

### Page1 / 4

ps1sol_ee550_fall08 - UNIVERSITY OF SOUTHERN CALIFORNIA...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online