Digital Logic Design-ch3 2010

Digital Logic Design-ch3 2010 - 9/23/10
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 Gate
Level
Minimiza4on
 Chapter
3
 EECE
256
 Dr.
Sidney
Fels
 Steven
Oldridge
 Topics
 •  •  •  •  •  •  Using
maps
to
simplify
Boolean
func4ons
 Product
of
sums
simplifica4on
 Don’t
cares
in
the
map
 NAND
and
NOR
 XOR
and
Parity
 a
brief
intro
to
HDL
 9/23/10
 (c)
S.
Fels,
since
2010
 2
 Using
geometry
to
simplify
 •  Remember
when
we
did:
 –  F
=
xy
+
xy’
=
x(y+y’)
=
x?


or
 –  F
=
xy
+
x’y
=
y(x+x’)
=
y?
 •  Finding
these
A+A’
groups
can
be
done
easily
 with
a
map
 •  But,
have
to
create
the
map
carefully
 •  Easiest
to
see
illustrated…
 9/23/10
 (c)
S.
Fels,
since
2010
 3
 1
 9/23/10
 n‐variable
maps,
Karnaugh
maps,
K‐ maps
 •  let’s
look
at
two
variable
maps
 9/23/10
 (c)
S.
Fels,
since
2010
 4
 n‐variable
maps,
Karnaugh
maps,
K‐ maps
 •  let’s
look
at
two
variable
maps
 9/23/10
 (c)
S.
Fels,
since
2010
 This
is
a
truth
table
 redrawn
 5
 n‐variable
maps,
Karnaugh
maps,
K‐ maps
 •  let’s
look
at
two
variable
maps
 9/23/10
 (c)
S.
Fels,
since
2010
 No4ce:
(x+x’)
here
 6
 2
 9/23/10
 K‐maps
 •  So,
if
we
have
a
func4on,
just
use
the
map
as
a
 truth
table
and
circle
the
ones

 –  adjacent
columns
or
rows
indicate
where
 simplifica4on
can
happen
 9/23/10
 (c)
S.
Fels,
since
2010
 7
 2
variable
map
example
 F
=
m3
 F
=
m1
+
m2
+
m3
 9/23/10
 (c)
S.
Fels,
since
2010
 8
 2
variable
map
example
 F
=
m3
 F
=
m1
+
m2
+
m3
 0
 0
 0
 0
 9/23/10
 (c)
S.
Fels,
since
2010
 9
 3
 9/23/10
 3
variable
map
example
 9/23/10
 (c)
S.
Fels,
since
2010
 10
 3
variable
map
example
 F
=
Σ(2,
3,
4,
5)
 x
 0
 0
 0
 0
 1
 1
 y
 0
 0
 1
 1
 0
 0
 1
 1
 z
 0
 1
 0
 1
 0
 1
 0
 1
 F
 0
 0
 1
 1
 1
 1
 0
 0
 0
 0
 0
 0
 1
 1
 9/23/10
 (c)
S.
Fels,
since
2010
 11
 3
variable
map
example
 F
=
Σ(2,
3,
4,
5)
 0
 0
 0
 0
 F
=
xy’
+
x’y
 9/23/10
 (c)
S.
Fels,
since
2010
 12
 4
 9/23/10
 3
variable
map
 •  F
=
Σ
(3,4,6,7)
 x
 0
 0
 0
 0
 1
 1
 1
 1
 y
 0
 0
 1
 1
 0
 0
 1
 1
 z
 0
 1
 0
 1
 0
 1
 0
 1
 F
 0
 0
 0
 1
 1
 0
 1
 1
 0
 0
 0
 0
 9/23/10
 (c)
S.
Fels,
since
2010
 13
 3
variable
map
 •  F
=
Σ
(3,4,6,7)
 x
 0
 0
 0
 0
 1
 1
 1
 1
 y
 0
 0
 1
 1
 0
 0
 1
 1
 z
 0
 1
 0
 1
 0
 1
 0
 1
 F
 0
 0
 0
 1
 1
 0
 1
 1
 0
 0
 0
 0
 9/23/10
 (c)
S.
Fels,
since
2010
 F
=
yz
+
xz’
 14
 More
points
to
remember
 •  cover
all
1’s
with
maximum
geometry
 –  rectangle
or
square
 –  watch
out
for
wrap
around
 •  don’t
double
count
if
not
needed
 9/23/10
 (c)
S.
Fels,
since
2010
 15
 5
 9/23/10
 4
variable
map
 Don’t
forget
Gray
coding
here
 9/23/10
 (c)
S.
Fels,
since
2010
 16
 4
variable
map
 •  F=Σ
(0,1,2,4,5,6,8,9,12,13,14)
 w
 x
 y
 z
 F
 0
 0
 0
 0
 1
 0
 0
 0
 1
 1
 0
 0
 1
 0
 1
 0
 0
 1
 1
 0
 0
 1
 0
 0
 1
 0
 1
 0
 1
 1
 0
 1
 1
 0
 1
 0
 1
 1
 1
 0
 1
 0
 0
 0
 1
 1
 0
 0
 1
 1
 1
 0
 1
 0
 0
 1
 0
 1
 1
 0
 1
 1
 0
 0
 1
 1
 1
 0
 1
 1
 1
 1
 1
 0
 1
 1
 1
 1
 1
 17
0
 0 0 0 0 0 9/23/10
 (c)
S.
Fels,
since
2010
 Prime
implicants
 •  largest
box
called
Prime
Implicant
 •  Prime
implicants
that
have
to
be
there
are
 called:
 –  essen4al
prime
implicants
 9/23/10
 (c)
S.
Fels,
since
2010
 18
 6
 9/23/10
 For
example
 •  F
=
Σ(0,2,3,5,7,8,9,10,11,13,15)
 9/23/10
 (c)
S.
Fels,
since
2010
 19
 You
can
easily
do
product‐of‐sum
too
 •  F(A,B,C,D)=Σ(0,1,2,5,8,9,10)
 –  circle
the
0’s
to
get
F’
and
use
de’Morgans
 9/23/10
 (c)
S.
Fels,
since
2010
 20
 You
can
easily
do
product‐of‐sum
too
 •  F’(A,B,C,D)=AB
+
CD
+
BD’
 •  
F(A,B,C,D)
=
F’’
=
(A’
+
B’)(C’
+
D’)(B’
+
D)
 9/23/10
 (c)
S.
Fels,
since
2010
 21
 7
 9/23/10
 Don’t
care
condi4ons
 •  Ojen,
there
are
parts
of
the
func4on
that
are
 unused
values
 –  i.e.,
BCD
only
uses
0‐9
encodings,
so
the
others
 don’t
maker
 –  in
this
case,
you
can
choose
either
a
0
or
1
for
it
to
 make
your
simplifica4on
beker
 9/23/10
 (c)
S.
Fels,
since
2010
 22
 Example
 •  F=Σ(1,3,7,11,15)
 •  d
=
Σ(0,2,5)
 9/23/10
 (c)
S.
Fels,
since
2010
 23
 don’t
care
Example
 •  Of
course,
if
you
want
product‐of‐sum
form,
 circle
0’s
and
x
to
get
minimal
forms
 F’
=
y’x
+
wy
+
yz’
 F
=
(y
+
x’)(w’
+
y’)(y’
+
z)
 9/23/10
 (c)
S.
Fels,
since
2010
 24
 8
 9/23/10
 NAND

and
NOR
 •  NAND:
Universal
gate
(any
digital
circuit
can
be
 implemented
using
only
NAND
gates)
 •  We
just
have
to
show
that
AND,
OR
and
NOT
 can
be
implemented
with
NANDs
 (AA)’
=
A’
 9/23/10
 (c)
S.
Fels,
since
2010
 25
 Another
way
to
look
at
it:
 •  two
ways
to
draw
a
NAND
gate
 •  Suggests
a
way
to
create
all
NAND
gate
 implementa4on
 –  move
the
bubbles
around
in
a
sum‐of‐products
 implementa4on…
 –  you
can
also
use
algebra
 (c)
S.
Fels,
since
2010
 26
 9/23/10
 Moving
the
inverters
for
all‐NAND
 F
=
AB+CD
 9/23/10
 (c)
S.
Fels,
since
2010
 27
 9
 9/23/10
 NAND
only
implementa4ons:
ex
1
 x
 0
 0
 0
 0
 1
 1
 1
 1
 y
 0
 0
 1
 1
 0
 0
 1
 1
 z
 0
 1
 0
 1
 0
 1
 0
 1
 F
 0
 1
 1
 1
 1
 1
 0
 1
 F
=
xy ’
+x’y
+
z
 9/23/10
 (c)
S.
Fels,
since
2010
 28
 mul4‐level
all‐NAND
 F
=
(AB’+A’B)(C+D’)
 9/23/10
 (c)
S.
Fels,
since
2010
 29
 all‐NOR
implementa4on
 •  Same
idea,
just
start
with
product‐of‐sum
 nota4on
 (x+x)’
=
x’
 9/23/10
 (c)
S.
Fels,
since
2010
 30
 10
 9/23/10
 all
NOR
implementa4on
 F=(AB’+A’B)(C+D’)
 A
 B’
 A’
 B
 C
 D’
 9/23/10
 (c)
S.
Fels,
since
2010
 31
 all
NOR
implementa4on
 F=(AB’+A’B)(C+D’)
 A’
 B
 A
 B’
 C
 D’
 9/23/10
 (c)
S.
Fels,
since
2010
 32
 XOR
and
Parity
 •  No4ce,
in
K‐map
we
some4me
get
a
checker
 board
pakern…
 9/23/10
 (c)
S.
Fels,
since
2010
 33
 11
 9/23/10
 XOR
 •  Exclusive‐OR
 x
 0
 0
 1
 1
 0
 y
 0
 1
 0
 1
 F
 0
 1
 1
 0
 –  x

⊕
y
=
x’y
+
xy’
 x
 1
 1
 0
 (c)
S.
Fels,
since
2010
 34
 y
 0
 1
 0
 1
 9/23/10
 3
input
XOR
–
Even/Odd
checker
 9/23/10
 (c)
S.
Fels,
since
2010
 35
 3
input
XOR
–
Even/Odd
checker
 F=Σ(1,3,5,7)
 odd
#
of
1’s
only
 9/23/10
 (c)
S.
Fels,
since
2010
 F=Σ(0,2,4,6)

 
even
number
of
1’s
only
 36
 12
 9/23/10
 Even/Odd
checker
extends
to
mul4ple
 inputs
 •  called
Parity
 •  Useful
for
error
checking
and
correc4ng
 9/23/10
 (c)
S.
Fels,
since
2010
 37
 Example:
Design
a
3‐bit
even
parity
 generator
 x
 0
 0
 0
 0
 1
 1
 1
 1
 y
 0
 0
 1
 1
 0
 0
 1
 1
 z
 0
 1
 0
 1
 0
 1
 0
 1
 P
 9/23/10
 (c)
S.
Fels,
since
2010
 38
 Example
1:
Design
a
3‐bit
even
parity
 generator
(total
bits
even)
 x
 0
 0
 0
 0
 1
 1
 1
 1
 y
 0
 0
 1
 1
 0
 0
 1
 1
 z
 0
 1
 0
 1
 0
 1
 0
 1
 P
 0
 1
 1
 0
 1
 0
 0
 1
 00
 01
 1
 0
 yz
 11
 0
 1
 10
 1
 0
 x
 1
 0
 0
 1
 P
=
x
+
y
+
z



 9/23/10
 Transmit
x,y,z,P
–
always
should
 have
even
#
of
bits
 (c)
S.
Fels,
since
2010
 39
 13
 9/23/10
 Example
2:
Design
a
3‐bit
w/even
 parity
checker
(4
bits

should
be
even)
 P
 0
 0
 0
 0
 0
 0
 0
 0
 1
 1
 1
 1
 1
 1
 1
 x
 0
 0
 0
 0
 1
 1
 1
 1
 0
 0
 0
 0
 1
 1
 1
 1
 y
 0
 0
 1
 1
 0
 0
 1
 1
 0
 0
 1
 1
 0
 0
 1
 1
 z
 0
 1
 0
 1
 0
 1
 0
 1
 0
 1
 0
 1
 0
 1
 0
 1
 E
 9/23/10
 1
 (c)
S.
Fels,
since
2010
 40
 Example
2:
Design
a
3‐bit
w/even
 parity
checker
(4
bits

should
be
even)
 P
 0
 0
 0
 0
 0
 0
 0
 0
 1
 1
 1
 1
 1
 1
 1
 x
 0
 0
 0
 0
 1
 1
 1
 1
 0
 0
 0
 0
 1
 1
 1
 1
 y
 0
 0
 1
 1
 0
 0
 1
 1
 0
 0
 1
 1
 0
 0
 1
 1
 z
 0
 1
 0
 1
 0
 1
 0
 1
 0
 1
 0
 1
 0
 1
 0
 1
 E
 0
 1
 1
 0
 1
 1
 0
 1
 1
 0
 0
 1
 0
 1
 1
 0
 00
 00
 0
 1
 0
 1
 01
 1
 0
 1
 0
 yz
 11
 0
 1
 0
 1
 10
 1
 0
 1
 0
 Px
 01
 11
 10
 E
=
P
+
x
+
y
+
z



 ‐
Outputs
a
1
if
the
data
has
an
odd
 number
of
1’s.
 (c)
S.
Fels,
since
2010
 41
 9/23/10
 1
 4bit
Even
Parity
Checker
 9/23/10
 (c)
S.
Fels,
since
2010
 42
 14
 9/23/10
 A
brief
intro
to
HDL
 •  most
combina4onal
circuits
are
complicated
 –  need
high
level
descrip4on
(HDL)
 •  •  •  •  communicate
between
designers
 simulate
on
computer
 use
computer
to
simplify
 describe
design
 •  Verilog
simulator
comes
with
your
text
 •  VHDL
another
language
 •  Other
descrip4on
languages
out
there
 –  good
to
be
familiar
with
a
few
 9/23/10
 (c)
S.
Fels,
since
2010
 43
 Simple
Circuit
 //
Verilog
model:
Simple_Circuit
 module
Simple_Circuit
(A,
B,
C,
D,
E);
 




output 
D,
E;
 




input
 
A,
B,
C;
 




wire 
 
w1;
 

and

 
G1
(w1,
A,
B);
//
Op4onal
gate
instance
 

not 
 
G2
(E,
C);
 

or 
 
G3
(D,
w1,
E);
 endmodule
 9/23/10
 (c)
S.
Fels,
since
2010
 44
 Simple
Circuit
with
prop‐delay
 //
Verilog
model
of
simple
circuit
with
propaga4on
delay
 module
Simple_Circuit_prop_delay
(A,
B,
C,
D,
E);
 

output
D,
E;
 

input 
 
A,
B,
C;
 

wire 
w1;
 
 

and

 
#(30)
G1
(w1,
A,
B);
 

not 
 
#(10)
G2
(E,
C);
 

or 
 
#(20)
G3
(D,
w1,
E);
 endmodule
 9/23/10
 (c)
S.
Fels,
since
2010
 45
 15
 9/23/10
 
ini4al
 



begin
 





A
=
1'bx;
B
=
1'bx;
C
=
1'bx;
 





A
=
1'b0;
B
=
1'b0;
C
=
1'b0;
 





#100
A
=
1'b1;
B
=
1'b1;
C
=
1'b1;
 





#100
$finish;
 


end
 Simple
Circuit
w/prop
output
 9/23/10
 (c)
S.
Fels,
since
2010
 46
 Summary
 •  •  •  •  •  •  maps
for
simplifying
Boolean
func4ons
 Product
of
sums
simplifica4on
 Don’t
cares
in
the
map
 NAND
and
NOR
 XOR
and
Parity
for
genera4ng
and
checking
 a
brief
intro
to
HDL
 –  combina4onal
circuits
can
get
very
complex
 9/23/10
 (c)
S.
Fels,
since
2010
 47
 16
 ...
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