Digital Logic Design-ch4 2010 - 10/13/10
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Unformatted text preview: 10/13/10
 Combina-onal
Logic
 Chapter
4
 EECE
256
 Dr.
Sidney
Fels
 Steven
Oldridge
 Topics
 •  Combina-onal
circuits
 •  Combina-onal
analysis
 •  Design
procedure
 –  simple
combined
to
make
complex
 –  adders,
subtractors,
converters
 –  decoders,
mul-plexers
 •  comb.
design
with
decoders
and
muxes
 10/13/10
 (c)
S.
Fels,
since
2010
 2
 Combina-on
Circuit
 •  Output
depends
only
on
present
value
of
 input
 NOTE:
No
Memory
or
feedback
paths
 10/13/10
 (c)
S.
Fels,
since
2010
 3
 1
 10/13/10
 Combina-on
Circuit
 •  What
happens
if
we
add
memory?
 10/13/10
 (c)
S.
Fels,
since
2010
 4
 Combina-on
Circuit
 •  What
happens
if
we
add
memory?
 Memory
Elements
 10/13/10
 Called
a:
Sequen&al
Circuit
 
‐
output
func-on
of
input
and
memory
 (c)
S.
Fels,
since
2010
 
‐
changes
over
-me
 5
 Combina-on
Circuit
 •  We’ll
focus
on
combina-onal
design
first
 –  useful
for
designing
how
memory
will
change
 when
making
sequen-al
circuits
 10/13/10
 (c)
S.
Fels,
since
2010
 6
 2
 10/13/10
 Combina-onal
Analysis
 •  Some-mes
need
to:
 –  confirm
circuit
does
what
it
is
supposed
to
 –  reverse
engineer
circuit
 •  Steps
(start
at
input
and
work
to
outputs):
 1.  label
all
outputs
that
are
fn’
of
inputs
and
derive
Boolean
 expression
 2.  label
all
outputs
that
fn’
of
inputs
and
labels
done
in
step
 1
and
derive
Boolean
expressions
 3.  repeat
un-l
all
outputs
have
Boolean
fn’
 4.  use
subs-tu-on
to
get
Boolean
fn’
based
only
on
inputs
 •  10/13/10
 fill
in
truth
table
 (c)
S.
Fels,
since
2010
 7
 Combina-onal
Analysis
 F2
=
AB+AC+BC
 T2
=
ABC
 T1
=
A+B+C
 10/13/10
 (c)
S.
Fels,
since
2010
 8
 Combina-onal
Analysis
 T3
=
T1

F2’
 F1
=
T2
+
T3
 10/13/10
 (c)
S.
Fels,
since
2010
 9
 3
 10/13/10
 Combina-onal
Analysis
 F1
=
ABC
+
T1

F2’
;
con-nue
subs-tu-ng
 F1
=
A’BC’
+
A’B’C
+
AB’C’
+
ABC
 10/13/10
 (c)
S.
Fels,
since
2010
 10
 Combina-onal
Design
 1.  2.  3.  4.  5.  Determine
the
number
of
inputs
and
outputs
 Assign
symbols
 Derive
the
truth
table
 Obtain
simplified
func-ons
for
each
output
 Draw
the
logic
diagram
 10/13/10
 (c)
S.
Fels,
since
2010
 11
 Adders
 •  most
fundamental
unit
in
computer
 •  add
two
numbers
 •  let’s
start
with
binary…
 10/13/10
 (c)
S.
Fels,
since
2010
 12
 4
 10/13/10
 ½
Adder
Design
 •  Step
1
–
#
of
inputs
and
outputs
 –  let’s
start
with
½
adder
first
 •  i.e.
let’s
not
worry
about
carry
in
just
yet
 0
 +
 sum
 carry
out
 0
 0
 0
 0
 1
 1
 0
 1
 0
 1
 0
 1
 1
 0
 1
 10/13/10
 (c)
S.
Fels,
since
2010
 13
 ½
Adder
Design
 •  Step
2
–
Assign
symbol
names
 0
 +
 sum
 carry
out
 0
 0
 0
 0
 1
 1
 0
 1
 0
 1
 0
 1
 1
 0
 1
 A
 B
 S
 C
 10/13/10
 (c)
S.
Fels,
since
2010
 14
 ½
Adder
Design
 •  Step
3
–
Derive
Truth
Table
 0
 +
 sum
 carry
out
 0
 0
 0
 0
 1
 1
 0
 1
 0
 1
 0
 1
 1
 0
 1
 A
 B
 S
 C
 A
 0
 0
 1
 10/13/10
 B
 0
 1
 0
 1
 S
 0
 1
 1
 0
 C
 0
 0
 0
 1
 (c)
S.
Fels,
since
2010
 15
 1
 5
 10/13/10
 ½
Adder
Design
 •  Step
4
–
Derive
simplified
form
 –  use
k‐maps,
Boolean
Algrebra,
etc.
 0
 +
 sum
 carry
out
 A
 0
 0
 1
 10/13/10
 0
 1
 1
 0
 C
 0
 0
 0
 1
 1
 0
 1
 0
 1
 1
 0
 1
 0
 0
 0
 B
 0
 1
 0
 1
 S
 0
 1
 1
 0
 A
 B
 S
 C
 S
=
A
+
B
 C
=
AB
 (c)
S.
Fels,
since
2010
 16
 1
 ½
Adder
Design
 •  Step
5
–
Draw
circuit
diagram
 0
 +
 sum
 carry
out
 0
 0
 0
 0
 1
 1
 0
 1
 0
 1
 0
 1
 1
 0
 1
 A
 B
 S
 C
 A
 0
 0
 1
 10/13/10
 B
 0
 1
 0
 1
 S
 0
 1
 1
 0
 C
 0
 0
 0
 1
 A
 B
 S
=
A
+
B
 C
=
AB
 (c)
S.
Fels,
since
2010
 17
 1
 Full
Adder
 •  We
need
to
worry
about
possible
carry‐in
 though
 x
 y
 Cin
 S
 Cout
 •  Same
procedure
 –  input:
x,
y,
Cin
 –  output:
S
and
Cout
 –  find
TT
 0
 0
 0
 0
 1
 1
 1
 1
 10/13/10
 (c)
S.
Fels,
since
2010
 0
 0
 1
 1
 0
 0
 1
 1
 0
 1
 0
 1
 0
 1
 0
 1
 18
 6
 10/13/10
 Full
Adder
 •  We
need
to
worry
about
possible
carry‐in
 though
 x
 y
 Cin
 S
 Cout
 •  Same
procedure
 –  input:
x,
y,
Cin
 –  output:
S
and
Cout
 –  find
TT
 0
 0
 0
 0
 1
 1
 1
 1
 10/13/10
 (c)
S.
Fels,
since
2010
 0
 0
 1
 1
 0
 0
 1
 1
 0
 1
 0
 1
 0
 1
 0
 1
 0
 1
 1
 0
 1
 0
 0
 1
 0
 0
 0
 1
 0
 1
 1
 1
 19
 x
 y
 0
 0
 1
 1
 0
 0
 1
 1
 Full
Adder
 •  Derive
Boolean
expressions
 y
Cin
 y
Cin
 Ci n
 0
 1
 0
 1
 0
 1
 0
 1
 S
 Co ut
 0
 1
 1
 0
 1
 0
 0
 1
 0
 0
 0
 1
 0
 1
 1
 1
 0
 0
 0
 0
 1
 1
 1
 1
 S
 Cin
 Cin
 Cout
 S
=
x’y’Cin
+
x’yCin’+xy’Cin’+xyCin
 Cout=
xy
+
xCin
+
yCin
 10/13/10
 (c)
S.
Fels,
since
2010
 20
 x
 y
 0
 0
 1
 1
 0
 0
 1
 1
 Full
Adder
 •  Derive
Boolean
expressions
 y
Cin
 y
Cin
 Ci n
 0
 1
 0
 1
 0
 1
 0
 1
 S
 Co ut
 0
 1
 1
 0
 1
 0
 0
 1
 0
 0
 0
 1
 0
 1
 1
 1
 0
 0
 0
 0
 1
 1
 1
 1
 S
 Cin
 Cin
 Cout
 S
=
x’y’Cin
+
x’yCin’+xy’Cin’+xyCin
=(x
+
y)
+
Cin
 Cout=
xy
+
xCin
+
yCin
=
(x
+
y)
Cin
+
xy
 10/13/10
 (c)
S.
Fels,
since
2010
 21
 7
 10/13/10
 Full
Adder
 •  xxx
 x
 y
 Cin
 10/13/10
 FA
 S
 ½
 adder
C
 ½
 S
 adder
 C
 S
 Cout
 22
 (c)
S.
Fels,
since
2010
 Cascade
them
for
4‐bit
Adder
 10/13/10
 (c)
S.
Fels,
since
2010
 23
 Cascade
them
for
a
parallel


















 4‐bit
Adder
 ripple
carry
adder
 How
big
is
the
truth
table?
 What’s
the
problem
with
this
circuit?
 10/13/10
 (c)
S.
Fels,
since
2010
 24
 8
 10/13/10
 Can
we
fix
this?
 •  we
need
to
compute
carry
bits
in
parallel
 rather
than
cascade
 •  Then,
use
some
½
adders
with
extra
circuits
to
 fix
the
sum
depending
upon
the
computed
 carries
 10/13/10
 (c)
S.
Fels,
since
2010
 25
 n‐bit
Carry
look‐ahead
Adder
 •  Recall
that
for
the
design
of
the
parallel
adder
to
work,
the
signal
must
 propagate
through
the
gates
before
the
correct
output
sum
is
available.
 •  Total
propaga&on
&me
=

 propaga&on
delay
of
a
typical
gate


x

the
number
of
gates
 •  Let’s
look
at
S3.

 –  Inputs
A3
and
B3
are
available
immediately.

 –  However,
C3
is
available
only
ager
C2
is
available.

 –  C2
has
to
wait
for
C1,
etc. 
 10/13/10
 (c)
S.
Fels,
since
2010
 26
 n‐bit
Carry
look‐ahead
Adder
 •  The
number
of
gate
levels
for
the
carry
to
 propagate
is
found
from
the
FA
circuit
 propaga-on
delay
 10/13/10
 (c)
S.
Fels,
since
2010
 27
 9
 10/13/10
 n‐bit
Carry
look‐ahead
Adder
 •  let’s
look
at
each
stage
to
see
how
we
know
 what
the
carry
is
 •  Pi
=
Ai
+
Bi
(carry
prop)
 •  Gi
=
AiBi


(carry
generate)
 •  Si
=
Pi
+
Ci
 •  Ci+1
=
Gi
+
PiCi
 10/13/10
 (c)
S.
Fels,
since
2010
 28
 n‐bit
Carry
look‐ahead
Adder
 •  let’s
look
at
each
stage
to
see
how
we
know
 what
the
carry
is
 •  Pi
=
Ai
+
Bi
(carry
prop)
 •  Gi
=
AiBi


(carry
generate)
 •  Si
=
Pi
+
Ci
 •  Ci+1
=
Gi
+
PiCi
 10/13/10
 Now,
calculate
each
stage’s
Carry
in
 terms
of
Cin
(i.e.
C0)
and
Ps
or
Gs.
 (c)
S.
Fels,
since
2010
 29
 n‐bit
Carry
look‐ahead
Adder
 •  C0
=
Cin
 •  C1
=
G0
+
P0C0
 •  C2
=

 •  C3
=
 10/13/10
 (c)
S.
Fels,
since
2010
 30
 10
 10/13/10
 n‐bit
Carry
look‐ahead
Adder
 •  C0
=
Cin
 •  C1
=
G0
+
P0C0
 •  C2
=
G1
+
P1C1
=
G1
+
P1(G0
+
P0C0)

 
 
 
 
 
 
 


=
G1+P1G0+P1P0C0
 •  C3
=
 10/13/10
 (c)
S.
Fels,
since
2010
 31
 n‐bit
Carry
look‐ahead
Adder
 •  C0
=
Cin
 •  C1
=
G0
+
P0C0
 •  C2
=
G1
+
P1C1
=
G1
+
P1(G0
+
P0C0)

 
 
 
 
 
 
 


=
G1+P1G0+P1P0C0
 •  C3
=
G2
+
P2C2
=
G2
+
P2(G1
+
P1G0
+
P1P0C0)
 
 
 
 
 
 
 
=
G2
+
P2G1
+
P1P2G0
+
P2P1P0C0
 So,
all
carries
are
now
computed
in
P2,
Gs
and
C0
 10/13/10
 (c)
S.
Fels,
since
2010
 32
 Carry
look‐ahead
circuit
 10/13/10
 (c)
S.
Fels,
since
2010
 33
 11
 10/13/10
 4
bit
Carry
look‐ahead
Adder
 •  Pi
=
Ai
+
Bi
 •  Gi
=
AiBi
 •  Si
=
Pi
+
Ci
 What
is
propaga-on
delay?
 10/13/10
 (c)
S.
Fels,
since
2010
 34
 Binary
Subtractor
 •  How
to
make
a
binary
subtractor?
 10/13/10
 (c)
S.
Fels,
since
2010
 35
 Binary
Subtractor
 •  How
to
make
a
binary
subtractor?
 –  remember:
2’s
complement
converts
subtrac-on
 into
addi-on
 –  so,
when
we
want
to
subtract,

 •  make
the
input
a
2’s
complement
number
 •  and
add
 –  check
for
overflow
 –  2’s
complement?
 –  invert
the
bits
+
1
 10/13/10
 (c)
S.
Fels,
since
2010
 36
 12
 10/13/10
 4‐bit
Binary
subtractor
 This
is
 really
a
 borrow
 now
 B3
 A3
 B2
 A2
 B1
 A1
 B0
 A0
 A‐B
 FA
 FA
 FA
 FA
 Cout
 C3
 D3
 D2
 C2
 D1
 C1
 D0
 1
 What
about
overflow?
 • 
if
unsigned
–
if
B
>
A;
look
at
Cout
 • 
if
signed
–
if
A
+ve
and
B
–ve
or
A
–ve
and
B
+ve
 ‐
look
at
Cout
and
sign
bit
(C3)
–
should
be
same 10/13/10
 (c)
S.
Fels,
since
2010
 37
 overflow
 case
1:
A,B
unsigned:
B>A
and
result
<
‐7
 0
 ‐
 1
 0
 0
 1
 1
 1
 1
 3 11
 ‐8
 unsigned
 0
 +
 1
 0
 1
 0
 1
 0
 1
 0
 0
 1
 1
 0
 3
 2’s
comp
of
11
 ‐8
 unsigned
 10/13/10
 (c)
S.
Fels,
since
2010
 38
 overflow
 case
2
‐
signed:
a
is
–ve,
b
is
+ve;
result
<
‐7,
i.e.
‐6
–
(+6)
 1
 ‐
 0
 0
 1
 1
 1
 0
 0
 ‐6
 ‐
(+6)
 signed
 1
 10/13/10
+
 0
 0
 1
 0
 ‐6
 +
(2’S
complement
of
+6)
 39
 1
 (c)
S.
Fels,
since
2010
 1
 0
 ‐12
–
but
4
bits
only
‐7
to
+7
 13
 10/13/10
 overflow
 case
3
‐
signed:
a
is
+ve,
b
is
‐ve;
result
>
+7,
i.e.
6
–
(‐6)
 0
 ‐
 1
 1
 0
 1
 1
 0
 0
 +6
 ‐
(‐6)
 signed
 0
 10/13/10
 1
 1
 1
 1
 0
 0
 +6
 +
(2’S
complement
of
‐6)
 +12
–
but
4
bits
only
‐7
to
+7
 40
 +
 0
 (c)
S.
Fels,
since
2010
 4‐bit
Binary
adder/subtractor
 •  We
can
put
this
together
to
make
a
more
 func-onal
element
 –  M
=
mode
for
add
(0)
or
subtract
(1)
 10/13/10
 (c)
S.
Fels,
since
2010
 41
 4‐bit
Binary
adder/subtractor
 10/13/10
 (c)
S.
Fels,
since
2010
 42
 14
 10/13/10
 Design
of
a
BCD
Adder
 •  Add
two
decimal
numbers

 –  (0‐9)+(0‐9)+(1)=
0‐19

‐
don’t
forget
carry
 •  How
to
begin?
 –  truth
table
 –  can
we
use
exis-ng
circuit
 •  binary
adder?
 10/13/10
 (c)
S.
Fels,
since
2010
 43
 Design
of
a
BCD
Adder
 If
we
just
put
decimal
numbers
in,
it
almost
works…
 10/13/10
 (c)
S.
Fels,
since
2010
 44
 BCD
adder
TT
 10/13/10
 (c)
S.
Fels,
since
2010
 45
 15
 10/13/10
 BCD
adder
TT
 same
as
binary
repn’
 need
decimal
carry
 10/13/10
 (c)
S.
Fels,
since
2010
 46
 BCD
adder
TT
 same
as
binary
repn’
 need
decimal
carry
 Z8Z2
 Z8Z4
 K4
 10/13/10
 C
=
K
+
Z8Z4
+
Z8Z2
 (c)
S.
Fels,
since
2010
 47
 BCD
adder
TT
 if
C=1;
need
to
add
6
to
the
Binary
sum
 
‐
so
we
need
another
binary
adder
 So,
we
can
now
draw
circuit
as
we
have
C
and
final
Sum
 10/13/10
 (c)
S.
Fels,
since
2010
 48
 16
 10/13/10
 BCD
adder
design
 10/13/10
 (c)
S.
Fels,
since
2010
 49
 BCD
adder
design
 10/13/10
 (c)
S.
Fels,
since
2010
 50
 Decoders
 •  A
binary
code
of
n
bits
can
represent
2n
 dis-nct
combina-ons
(or
unique
 “cases”).
 Decoder:
a
combina-onal
circuit
that
 converts
n
binary
lines
into
2n
unique
 output
lines
 Example:
a
3‐to‐8
line
decoder
 –  3
inputs
are
decoded
to
8
outputs
–
 represen-ng
the
8
minterms
 Minterms
 •  •  10/13/10
 (c)
S.
Fels,
since
2010
 51
 17
 10/13/10
 Decoders
 •  •  A
binary
code
of
n
bits
can
represent
2n
 dis-nct
combina-ons
(or
unique
 “cases”).
 Decoder:
a
combina-onal
circuit
that
 converts
n
binary
lines
into
2n
unique
 output
lines
 Example:
a
3‐to‐8
line
decoder
 –  3
inputs
are
decoded
to
8
outputs
–
 represen-ng
the
8
minterms
 Minterms
 •  x
 y
 z
 D0
 3x8
 Decoder
 D7
 10/13/10
 (c)
S.
Fels,
since
2010
 52
 Decoder
design
 Inputs
 x
 0
 0
 0
 0
 1
 1
 1
 1
 Outputs
 z
 0
 1
 0
 1
 0
 1
 0
 1
 y
 0
 0
 1
 1
 0
 0
 1
 1
 D0
 1
 0
 0
 0
 0
 0
 0
 0
 D1
 0
 1
 0
 0
 0
 0
 0
 0
 D2
 0
 0
 1
 0
 0
 0
 0
 0
 D3
 0
 0
 0
 1
 0
 0
 0
 0
 D4
 0
 0
 0
 0
 1
 0
 0
 0
 D5
 0
 0
 0
 0
 0
 1
 0
 0
 D6
 0
 0
 0
 0
 0
 0
 1
 0
 D7
 0
 0
 0
 0
 0
 0
 0
 1
 10/13/10
 (c)
S.
Fels,
since
2010
 53
 Decoder
truth
table
 Inputs
 x
 0
 0
 0
 0
 1
 1
 1
 1
 Outputs
 z
 0
 1
 0
 1
 0
 1
 0
 1
 y
 0
 0
 1
 1
 0
 0
 1
 1
 D0
 1
 0
 0
 0
 0
 0
 0
 0
 D1
 0
 1
 0
 0
 0
 0
 0
 0
 D2
 0
 0
 1
 0
 0
 0
 0
 0
 D3
 0
 0
 0
 1
 0
 0
 0
 0
 D4
 0
 0
 0
 0
 1
 0
 0
 0
 D5
 0
 0
 0
 0
 0
 1
 0
 0
 D6
 0
 0
 0
 0
 0
 0
 1
 0
 D7
 0
 0
 0
 0
 0
 0
 0
 1
 10/13/10
 (c)
S.
Fels,
since
2010
 54
 18
 10/13/10
 Decoder
with
NAND
 10/13/10
 (c)
S.
Fels,
since
2010
 55
 NAND
Decoder
with
enable
 Now
we
can
combine
them
to
get
bigger
ones.
 10/13/10
 (c)
S.
Fels,
since
2010
 56
 Combining
Decoders
 10/13/10
 4x16
Decoder
–
check
specs
whether
inverted
or
not
 (c)
S.
Fels,
since
2010
 57
 19
 10/13/10
 Boolean
Func-ons
with
Decoders
 •  since
we
have
all
minterms
it
is
easy
to
 combine
them
for
our
Boolean
func-ons
 •  For
example:
 –  S
=
Σ(1,
2,
4,
7)
 –  C
=
Σ(3,
5,
6,
7)
 10/13/10
 (c)
S.
Fels,
since
2010
 58
 Boolean
Func-on
with
Decoders
 10/13/10
 (c)
S.
Fels,
since
2010
 59
 Encoders
 •  Inverse
opera-on
of
a
decoder

 –  It
has
2n
inputs
and
generates
n
codewords
 •  Example:
Design
a
8
x
3
encoder
 10/13/10
 (c)
S.
Fels,
since
2010
 60
 20
 10/13/10
 8x3
Encoders
 X
=
D4
+
D5
+
D6
+
D7
 Y
=
D2
+
D3
+
D6
+
D7
 Z
=
D1
+
D3
+
D5
+
D7
 10/13/10
 (c)
S.
Fels,
since
2010
 61
 8x3
Encoders
 X
=
D4
+
D5
+
D6
+
D7
 Y
=
D2
+
D3
+
D6
+
D7
 Z
=
D1
+
D3
+
D5
+
D7
 10/13/10
 What’s
the
problem
here?
 (c)
S.
Fels,
since
2010
 62
 Priority
Encoder
 •  For
the
other
inputs
use
priority
to
determine
 output
 –  i.e.
D3
takes
priority
over
D2;
D2
over
D1
etc.
 10/13/10
 (c)
S.
Fels,
since
2010
 63
 21
 10/13/10
 Priority
Encoder
 10/13/10
 (c)
S.
Fels,
since
2010
 64
 Priority
Encoder
 1
 No-ce,
we
can
use
the
don’t
cares
to
design
this.
 10/13/10
 (c)
S.
Fels,
since
2010
 65
 Priority
Encoder
 10/13/10
 (c)
S.
Fels,
since
2010
 66
 22
 10/13/10
 Mul-plexers
 •  A
mul-plexer
selects
one
of
many
inputs
and
 directs
it
to
the
output.
 ch1
 ch2
 chn
 Transmission
 line
 •  The
selec-on
may
be
controlled
by
“select
lines”
 •  Normally
2n
input
lines:
n
select
lines
 10/13/10
 (c)
S.
Fels,
since
2010
 67
 Mul-plexers
 •  Example:
2
x
1
mul-plexer
 •  How
to
design?
 –  let’s
design
4x1
MUX
 –  code
redirects
input
 •  use
AND
gate
with
minterm
 •  like
decoder
with
AND
gate
 (c)
S.
Fels,
since
2010
 68
 10/13/10
 4x1
MUX
 10/13/10
 (c)
S.
Fels,
since
2010
 69
 23
 10/13/10
 Using
MUXes
for
Boolean
func-ons
 •  Use
a
mul-plexer
to
implement
the
following
 func-on:
 –  F
=
x’y’z
+
x’yz’
+
xy’z
+
xyz
 •  Idea:
 –  no-ce
that
MUX
isa
decoder
+
OR
gate
 –  use
the
selector
to
direct
correct
value
to
output
 10/13/10
 (c)
S.
Fels,
since
2010
 70
 Using
MUXes
for
Boolean
func-ons
 •  Example
 –  F(x,y,z)
=
Σ(1,2,6,7)
 10/13/10
 (c)
S.
Fels,
since
2010
 71
 Using
MUXes
for
Boolean
func-ons
 •  Example
 –  F(x,y,z)
=
Σ(1,2,6,7)
 10/13/10
 (c)
S.
Fels,
since
2010
 72
 24
 10/13/10
 Using
MUXes
for
Boolean
func-ons
 10/13/10
 (c)
S.
Fels,
since
2010
 73
 Using
MUX
for
Boolean
Fn’
 •  Design
a
Full‐adder

 –  S(x,y,z)
=
Σ(1,2,4,7);
C(x,y,z)
=
Σ(1,2,4,7)
 x
 0
 0
 0
 0
 1
 1
 1
 1
 y
 0
 0
 1
 1
 0
 0
 1
 1
 z
 0
 1
 0
 1
 0
 1
 0
 1
 S
 C
 10/13/10
 (c)
S.
Fels,
since
2010
 74
 Using
MUX
for
Boolean
Fn’
 •  Design
a
Full‐adder

 –  S(x,y,z)
=
Σ(1,2,4,7);
C(x,y,z)
=
Σ(3,5,6,7)
 x
 0
 0
 0
 0
 1
 1
 1
 1
 y
 0
 0
 1
 1
 0
 0
 1
 1
 z
 0
 1
 0
 1
 0
 1
 0
 1
 S
 0
 1
 1
 0
 1
 0
 0
 1
 C
 0
 0
 0
 1
 0
 1
 1
 1
 10/13/10
 (c)
S.
Fels,
since
2010
 75
 25
 10/13/10
 Using
MUX
for
Boolean
Fn’
 •  Design
a
Full‐adder

 –  S(x,y,z)
=
Σ(1,2,4,7);
C(x,y,z)
=
Σ(3,5,6,7)
 x
 0
 0
 0
 0
 1
 1
 1
 1
 y
 0
 0
 1
 1
 0
 0
 1
 1
 z
 0
 1
 0
 1
 0
 1
 0
 1
 S
 0
 1
 1
 0
 1
 0
 0
 1
 C
 0
 0
 0
 1
 0
 1
 1
 1
 Sm
 z
 z
 z’
 z’
 z’
 z’
 z
 z
 Cm
 0
 0
 z
 z
 z
 z
 1
 1
 z
 z’
 z’
 z
 S
 0
 z
 z
 C
 10/13/10
 (c)
S.
Fels,
since
2010
 76
 Summary
 •  Combina-onal
circuits
 •  Combina-onal
analysis
 •  Design
procedure
 –  simple
combined
to
make
complex
 –  adders,
subtractors,
converters
 –  decoders,
mul-plexers
 •  comb.
design
with
decoders
and
muxes
 10/13/10
 (c)
S.
Fels,
since
2010
 77
 26
 ...
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This note was uploaded on 12/21/2010 for the course EECE EECE 256 taught by Professor Sidney during the Spring '10 term at The University of British Columbia.

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