Digital Logic Design-ch5 2010

# Digital Logic Design-ch5 2010 - Synchronous Sequential...

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1 Synchronous Sequential Logic Chapter 5 Steve Oldridge Dr. Sidney Fels 10/6/2010 c Steve Oldridge since 2010 2 Topics • Sequential Circuits – What happens when we add memory? • Latches • Flip-Flops • Clocks • State Tables – Reduction of States 10/6/2010 c Steve Oldridge since 2010 3 Sequential Circuits

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2 10/6/2010 c Steve Oldridge since 2010 4 Synchronous Sequential Circuits 10/6/2010 c Steve Oldridge since 2010 5 Latches • Maintains a State – Output is the same as long as there is power – Memory! • SR Latch – NOR – NAND • D Latch 10/6/2010 c Steve Oldridge since 2010 6 SR Latch
3 10/6/2010 c Steve Oldridge since 2010 7 SR Latch Truth Table 10/6/2010 c Steve Oldridge since 2010 8 SR Latch Truth Table (NAND edition) 10/6/2010 c Steve Oldridge since 2010 9 Controlling SR Latches • We don’t always want the circuit to change immediately

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4 10/6/2010 c Steve Oldridge since 2010 10 • What was the problem with latches? – If set and reset are both active… – Q = Q` which is impossible • How can we overcome that? – R = S` 10/6/2010 c Steve Oldridge since 2010 11 D Latch (Transparent Latch) 10/6/2010 c Steve Oldridge since 2010 12 Symbols for Latches
5 10/6/2010 c Steve Oldridge since 2010 13 • Latch • FlipFlop 10/6/2010 c Steve Oldridge since 2010 14 Edge triggered D Flip-Flop 10/6/2010 c Steve Oldridge since 2010 15 Positive Edge Trigger

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6 10/6/2010 c Steve Oldridge since 2010 16 D Flip-Flop 10/6/2010 c Steve Oldridge since 2010 17 Other Flip-Flops? • What is the main function of a flip-flop?
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## This note was uploaded on 12/21/2010 for the course EECE EECE 256 taught by Professor Sidney during the Spring '10 term at UBC.

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Digital Logic Design-ch5 2010 - Synchronous Sequential...

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