Digital Logic Design-ch8 2010

# Digital Logic Design-ch8 2010 - Register Transfer Level...

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1 Register Transfer Level Design Chapter 8 Steve Oldridge Dr. Sidney Fels Topics • RTL Notation • RTL in HDL • Algorithmic State Machines • Sequential Binary Multiplier – Control Logic – HDL • Design with Multiplexors • Race-Free Design • Latch-Free Design Register Transfer Level Notation • A Circuit is described as: – The set of registers in the system – Operations performed on the data in those registers – Control that supervises the sequence of operations

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2 RTL Notation Examples • R2 R1 • If (T1 = 1) then R2 R1 • If (T3 = 1) then (R2 R1, R1 R2) • R1 R1 + R2 • R3 R3 + 1 • R4 shr R4 • R5 0 RTL in HDL • Assign S = A + B • Always @(A,B) S = A+B; • Always @(negedge clock) Begin RA = RA + RB; RD = RA; End • Always @(negedge clock) Begin RA <= RA + RB; RD <= RA; End Arithmetic Operators
3 Logic Operators Shift Operators Relational Operators

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4 Order of Operations Looping • Repeat (n) • Forever • While (condition) • For (k=0; k<=3; k++) Looping Example • Initial Begin clock = 1’b0; repeat (16) // creates an 8 cycle clock #5 clock = ~clock; end;
5 Logic Synthesis Process Algorithmic State Machines ASM Charts

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6 ASM Chart Example ASM Block Simplifications of ASM
7 Timing Considerations Algorithmic State Machine and Datapath Chart (ASMD) ASMD Example

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8 Timing Sequence Controller and Hardware Datapath RTL via State Diagrams
9 State Table Controller Circuitry HDL for our Example module Design_Example_RTL // carefully consider unused state code implications for output and next state ( output reg [3:0] A, output reg E, F, input Start, clock, reset_b ); reg [1: 0] state, next_state; reg clr_E, set_E, clr_F, set_F, clr_A_F, incr_A; parameter S_idle = 2'b00, S_1 = 2'b01, S_2 = 2'b11; wire A2 = A[2], A3 = A[3];

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10 // control unit always @ (posedge clock, negedge reset_b) if (reset_b ==0) state <= S_idle; else state <= next_state; always @ (state, Start, A2, A3) begin next_state = state; clr_E = 0; set_E = 0; clr_A_F = 0; set_F = 0; incr_A = 0; case (state) S_idle: if (Start) begin next_state = S_1; clr_A_F = 1; end S_1: begin incr_A = 1; if (A2 == 0) clr_E = 1; else
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## This note was uploaded on 12/21/2010 for the course EECE EECE 256 taught by Professor Sidney during the Spring '10 term at UBC.

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Digital Logic Design-ch8 2010 - Register Transfer Level...

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