Unformatted text preview: Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Section 5 MetalOxideSemiconductor FieldEffect Transistors (MOSFETs)
Part 2: Smallsignal MOSFET analysis Sedra/Smith, 4.44.7, 4.10, 10.3 J. Schwartz, 2007 FETs 5.2.1 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Outline of Section 5
• • • • • • • • • 5.1 Intro to MOS Field Effect Transistor (MOSFET) 5.2 NMOS FET 5.3 PMOS FET 5.4 DC Analysis of MOSFET Circuits 5.5 MOSFET Amplifier 5.6 MOSFET Small Signal Model 5.7 MOSFET Integrated Circuits 5.8 CSA, CGA, CDA 5.9 CMOS Inverter & MOS Digital Logic J. Schwartz, 2007 FETs 5.2.2 Page 1 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Small Signal Analysis
• Gate input has DC and AC components • So will the drain voltage and current • Develop small signal model J. Schwartz, 2007 FETs 5.2.3 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Operating Point ID vs VGS
• DC analysis, AC sources off • Operating point determined by VGSVt in saturation
ID
Operating Point VGS
J. Schwartz, 2007 FETs 5.2.4 Page 2 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Small Signal Superposition – ID vs VGS
ID
Operating Point Consider superposition of an AC signal at the DC operating point Slope of idvgs curve at operating defined as MOSFET transconductance, gm
gm ≡ ∂I D ∂VGS ≈
OP ΔI D ΔVGS J. Schwartz, 2007 VGS FETs 5.2.5 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics MOSFET Transconductance – gm
• To derive an expression for gm: • Start with full ID equation • Take derivative and simplify gm ≡ ∂iD ∂vGS iD = I D ′ iD = 1 k n 2 W (vGS − Vt )2 (1 + λ ⋅VDS ) L ∂iD W ′ = k n (VGS − Vt )(1 + λ ⋅ VDS ) ∂vGS L gm =
J. Schwartz, 2007 2⋅ ID VGS − Vt 2⋅ ID (VGS − Vt )
FETs 5.2.6 Page 3 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Summary of gm
• Sedra & Smith use several expressions for gm gm = 2⋅ ID VGS − Vt
W (VGS − Vt )(1 + λ ⋅VDS ) L ′ g m = kn ′ g m = 2k n
J. Schwartz, 2007 W 1 + λ ⋅ VDS I D L
FETs 5.2.7 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Basic MOSFET Amplifier Operation
• Apply small signal at gate: vgs • Results in signal current flow at drain id; gm proportionality constant • Signal current through RD produces output voltage • Output signal voltage equal to: vd = gmvvgsRD
J. Schwartz, 2007 FETs 5.2.8 Page 4 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Outline of Section 5
• • • • • • • • • 5.1 Intro to MOS Field Effect Transistor (MOSFET) 5.2 NMOS FET 5.3 PMOS FET 5.4 DC Analysis of MOSFET Circuits 5.5 MOSFET Amplifier 5.6 MOSFET Small Signal Model 5.7 MOSFET Integrated Circuits 5.8 CSA, CGA, CDA 5.9 CMOS Inverter & MOS Digital Logic J. Schwartz, 2007 FETs 5.2.9 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Small Signal Modeling
• In response to signal input between gate and source, vgs, signal current flows in drain, id Still to be determined:  output resistance (ro)?  input resistance?  body terminal?
J. Schwartz, 2007 FETs 5.2.10 Page 5 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Small Signal Output Resistance
• Since the characteristic curve for IDVDS indicates a slope when in saturation, there is an output resistance associated with the drainsource nodes.
ID
Linear over a wide range ! An output resistance can be calculated for a given VGSVt The Slope is the inverse of the MOSFET output resistance rO. ⎡ ∂I ro ≡ ⎢ D ⎢ ∂VDS ⎣
J. Schwartz, 2007 ⎤ ΔVDS ⎥≈ ΔI D OP ⎥ ⎦ −1 From Channel Length Modulation (CLM) VDS
FETs 5.2.11 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Output Resistance – ro
• To derive an expression for ro: • Start with full saturation ID equation • Take derivative and simplify
Note: λ = 1/VA
⎡ ∂I ro ≡ ⎢ D ⎢ ∂VDS ⎣
′ I D = 1 kn 2 ⎤ ⎥ OP ⎥ ⎦ −1 W (VGS − Vt )2 (1 + λ ⋅VDS ) L ∂I D W 2 ′ = 1 k n (VGS − Vt ) ⋅ λ ∂VDS 2 L ID ID ∂I D λ ⋅ ID = = = ≈ λ ⋅ ID ∂VDS 1 + λ ⋅VDS 1 + V VA + VDS DS λ ro ≈
J. Schwartz, 2007 1 λ ⋅ ID
FETs 5.2.12 Page 6 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Small Signal Modeling
• The slope of the IDVDS curve indicates a finite resistance between the drain and the source. J. Schwartz, 2007 FETs 5.2.13 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics The MOSFET TModel
• When input signal (voltage or current) is applied at source terminal, use the Tmodel. • Nonzero signal current flows in source • Input resistance looking into source is finite • Need to determine source resistance parameter
J. Schwartz, 2007 IG=0 How describe source input resistance ?
FETs 5.2.14 Page 7 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Source Resistance for Tmodel
• Desire relationship between source current and gatesource voltage; analogous to emitter current and baseemitter voltage. • Can identify a V=IR relationship • Define rs as the input resistance looking into the source • Can compute: rs = vgs/is • Since is = id, and id = gmvgs, recognize that rs=1/gm=vgs/is
J. Schwartz, 2007 FETs 5.2.15 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics The MOSFET T Small Signal Model IG=0 IG=0 J. Schwartz, 2007 FETs 5.2.16 Page 8 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics The Body Effect – Small Signal
• Recall that DC Body effect occurs because Body and Source not always maintained at same potential • The same thing can apply to AC analysis – The body terminal always connected to most negative DC power supply; – Body terminal will always be at signal ground. – The small signal body effect occurs when the source is not at signal ground. – Result: the body behaves like a second – but weaker – gate
J. Schwartz, 2007 FETs 5.2.17 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Modeling the Small Signal Body Effect
• Consider effect of small changes in VBS on ID: • VBS dependence is in Vt: • Start with full ID expression • Take derivative and simplify
∂I D ∂VBS
OP Vt = Vt 0 + γ
′ I D = 1 kn 2 ( 2φ f + VSB − 2φ f ) W (VGS − Vt )2 (1 + λ ⋅VDS ) L ∂I D ∂I ∂Vt W −1 ⎡ ⎤ ′ = D⋅ = 2 ⋅ 1 k n (VGS − Vt )(1 + λ ⋅ VDS )(− 1)⎥ ⋅ 1 ⋅ γ (2φ f + VSB ) 2 (− 1) 2 ∂VBS ∂Vt ∂VBS ⎢ 2 L ⎣ ⎦ [ Body transconductance
⎡γ 1 =⎢ ⎢ 2 2φ f + VSB ⎣
J. Schwartz, 2007 ⎤ ⎥ ⋅ gm = χ ⋅ gm ⎥ ⎦ g mb = χ ⋅ g m γ χ= ⋅
2 1 2φ f + VSB
FETs 5.2.18 Page 9 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Hybridπ Small Signal Model J. Schwartz, 2007 • AC Body effect: another VCCS (dependent on gmb) in parallel with the one dependent on gm • T model generally not used when modeling Body effect, regardless of circuit topology
FETs 5.2.19 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics pMOS Small Signal Model
• Small signal model for PMOS is identical to that for NMOS • Be careful of location of G, D, and S terminals
– DC current flows one way, signal current flows the other way ID J. Schwartz, 2007 FETs 5.2.20 Page 10 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Common Source MOSFET Amplifier RLRD J. Schwartz, 2007 FETs 5.2.21 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Small Signal Operation
• Small signal analysis requires the use of “small” signals to be valid • Start with expression for drain current:
′ iD = 1 k n 2 • Substitute vGS = VGS + vgs, iD = ID + id • Expand quadratic term:
′ I D + id = 1 k n 2 W (vGS − Vt )2 (1 + λVDS ) L (V GS + v gs − Vt ) = (VGS − Vt ) + v gs
2 2 W (VGS + vgs − Vt )2 (1 + λVDS ) L [ 2 2 = (VGS − Vt ) + 2v gs (VGS − Vt ) + v gs v gs << 2(VGS − Vt )
J. Schwartz, 2007 FETs 5.2.22 Page 11 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Outline of Section 5
• • • • • • • • • 5.1 Intro to MOS Field Effect Transistor (MOSFET) 5.2 NMOS FET 5.3 PMOS FET 5.4 DC Analysis of MOSFET Circuits 5.5 MOSFET Amplifier 5.6 MOSFET Small Signal Model 5.7 MOSFET Integrated Circuits 5.8 CSA, CGA, CDA 5.9 CMOS Inverter & MOS Digital Logic J. Schwartz, 2007 FETs 5.2.23 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics MOSFET Design Space
• Modern integrated circuits use MOSFETs extensively
– Very high densities of transistors – up to 109 transistors/cm2 in some ULSI memory arrays. – Offchip discrete resistors and capacitors are NOT commonly used – Onchip resistors and capacitors generally small – Multistage amplifiers are usually DCcoupled • Transistors used wherever possible to implement current sources, resistors, capacitors, J. Schwartz, 2007 FETs 5.2.24 Page 12 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Using MOSFETs to implement R’s and C’s
• Resistors:
Active Loads (large R’s) Diodeconnected loads (small R’s) MOSFET TriodeRegion (moderate R’s) • Capacitors
Most obvious is the gatebody capacitor Can be used to have variablecapacitors as well • Current Mirrors
J. Schwartz, 2007 FETs 5.2.25 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics MOSFET Active Loads
• MOSFETs used as an active load for high resistances:
– MOSFET is held in saturation with the source and gate held at a constant DC voltage 1 ro = – Drain connected to circuit λ ⋅ ID – ro is inversely proportional to ID vgs = 0 gmvgs = 0
J. Schwartz, 2007 FETs 5.2.26 Page 13 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics DiodeConnected MOSFETs
• The Drain is directly connected to Gate, and therefore it can only be operated in saturation (or cutoff) • Source Absorption : J. Schwartz, 2007 FETs 5.2.27 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics MOSFET Current Mirrors
• Used extensively in MOSFET IC applications • Neglected ro. • Since there is no gate current, the drain currents of M1 and M2 are identical VX 0 VGS + 0 + VGS   J. Schwartz, 2007 FETs 5.2.28 Page 14 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Current Mirror DC Analysis
• The width and length (the W/L aspect ratio) of MOSFETs can be designed almost freely • Since the W/L of M1 and M2 need not be the same, the size ratios can affect current ratios
I REF W 2 ′ = 1 k n 1 (VGS − Vt ) 2 L1 I W1 L1 VGS + + VGS W2 L2 W 2 ′ I = 1 k n 2 (VGS − Vt ) 2 L2  I
J. Schwartz, 2007 I REF = W2 L1 ⋅ L2 W1 FETs 5.2.29 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Current Scaling
• Ratio of aspect ratios can be selected to achieve nearly any scale factor I/IREF W L W L W L W L J. Schwartz, 2007 FETs 5.2.30 Page 15 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Current Mirroring – Pushing and Pulling J. Schwartz, 2007 FETs 5.2.31 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Small Signal
• Transistor M1 is diode connected and acts like a resistor to s.s. ground. • Similar to BJT small signal result, namely r02 is the only element that remains in small signal circuit. J. Schwartz, 2007 FETs 5.2.32 Page 16 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Outline of Section 5
• • • • • • • • • 5.1 Intro to MOS Field Effect Transistor (MOSFET) 5.2 NMOS FET 5.3 PMOS FET 5.4 DC Analysis of MOSFET Circuits 5.5 MOSFET Amplifier 5.6 MOSFET Small Signal Model 5.7 MOSFET Integrated Circuits 5.8 CSA, CGA, CDA 5.9 CMOS Inverter & MOS Digital Logic J. Schwartz, 2007 FETs 5.2.33 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics DC and AC  BodyEffect / CLM
Three types of analysis: Neglect DC BodyEffect & DC CLM
Use DC BodyEffect / Neglect DC CLM Use DC BodyEffect / Use DC CLM DC Analysis
Use whatever DC values for V and I in the smallsignal analysis Three types of analysis: Neglect AC BodyEffect & AC CLM
Use AC BodyEffect / Neglect AC CLM Use AC BodyEffect / Use CLM
J. Schwartz, 2007 AC Analysis (smallsignal)
FETs 5.2.34 Page 17 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Common Source Amplifier (CSA)
• Current source I implemented with pMOS current mirror. • Current mirror provides active load at drain • Source terminal grounded – no DC or AC Body effect J. Schwartz, 2007 FETs 5.2.35 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CSA with Current Mirror J. Schwartz, 2007 FETs 5.2.36 Page 18 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CSA Small Signal Analysis
• From MOSFET CurrentMirror: only ro2 appears in analysis v gs1 = vi
vout = − g m1 (ro1 ro 2 )v gs1
AV =
J. Schwartz, 2007 vout = − g m1 (ro1 ro 2 ) vi
FETs 5.2.37 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CSA Input/Output Resistance
• Input Resistance RIN ⇒ ∞
• Output resistance vgs1 = 0 gm1vgs1 = 0 ROUT = ro1 ro 2
J. Schwartz, 2007 FETs 5.2.38 Page 19 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Common Gate Amplifier (CGA)
• A pMOS current mirror is used as IREF including the output resistance. • The gate terminal held at a DC voltage. • Since source terminal not at signal ground, the body effect is present.
+ vi ~ Typically used as second stage of a multistage amplifier circuit
FETs 5.2.39 J. Schwartz, 2007 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CGA – DC Analysis
• DC voltage at the source terminal (VS) must be obtained from driving the current IREF through the transistor. • This assumes that the signal input voltage source vi is set to zero for DC • RI is part of the source voltage • Solve for VO, with VS and VG known, and including CLM + vi  ~ ′ I = 1 kn 2 W (VG − VS − Vt )2 [1 + λ ⋅ (VO − VS )] L
FETs 5.2.40 J. Schwartz, 2007 Page 20 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CGA – Signal Analysis
• Replace current source with output resistance ro2 Choice of analysis: Neglect AC BodyEffect & CLM
Use AC BodyEffect / Neglect CLM Use AC BodyEffect / Use CLM
J. Schwartz, 2007 ~ + vi  FETs 5.2.41 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CGA – No Body Effect or CLM vo = − g m v gs ⋅ ro 2
i=0 v gs = − 1 g m1 1 + RI g m1 vI + vi J. Schwartz, 2007 ~ AV = vo ro 2 = 1 vI + RI gm
FETs 5.2.42 Page 21 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CGA – RIN & ROUT, No Body Effect or CLM
RIN =
ROUT 1 g m1 Note: Ri, as a part of the source, is not included in this calculation RIN + vi J. Schwartz, 2007 vi = 0
~ ROUT = ro 2 FETs 5.2.43 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CGA – With Body Effect & no CLM
Solve at vx first:
vX
+ vs ~ RIN vbs1 = v gs1 = −v x
vo = −(g m1v gs1 + g mb1vbs1 )ro 2 vo = (g m1v x + g mb1vx )ro 2
AV =
AV = Include RI and solve for total voltage gain in term of RIN
J. Schwartz, 2007 vo = ( g m1 + g mb1 )ro 2 vx vout vout v x RIN = ⋅ = ( g m + g mb )ro 2 ⋅ vi v x vi RIN + RI
FETs 5.2.44 Page 22 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CGA – RIN With Body Effect & no CLM
iX vX
iIN RIN vbs1 = v gs1 = −v x
iin = ( g m1 + g mb1 )vx
RIN = 1 g m1 + g mb1
Rout = ro2
can now apply Rin to AV on previous slide
FETs 5.2.45 Neglect Input Voltage Source
J. Schwartz, 2007 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CGA – With Body Effect & with CLM
Solve at vx first:
vX
+ vs ~ RIN vbs1 = v gs1 = −v x
⎛ v −v ⎞ vo = −⎜ g m1v gs1 + g mb1vbs1 + o x ⎟ro 2 ⎜ ro1 ⎟ ⎝ ⎠ ⎛ 1⎞ r ⎟ro 2 vo (1 + o 2 ) = vx ⎜ g m1 + g mb1 + ⎜ ro1 r o1 ⎟ ⎝ ⎠ Include RI and solve for total voltage gain in term of RIN
J. Schwartz, 2007 ⎛ 1⎞ ⎜ g m1 + g mb1 + ⎟ro 2 ⎜ ro1 ⎟ v ⎠ ⋅ RIN AV = o = ⎝ ro1 RIN + RI vi 1+ ro 2 FETs 5.2.46 Page 23 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CGA – RIN With Body Effect & CLM
iX vX RIN vo = ix ⋅ ro 2
ix = ( g m1 + g mb1 )v x + v x − vo ro1 Neglect Input Voltage Source
J. Schwartz, 2007 RIN can now apply Rin to AV on previous slide r 1 + o2 vx ro1 == 1 ix + g m1 + g mb1 ro1 Rout = ro2ro1
FETs 5.2.47 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Common Drain Amplifier (CDA)
• A nMOS current mirror is used as IREF including the output resistance. • Voltage signal source DCcoupled to gate terminal • Drain terminal held at a DC voltage • Since source terminal not at signal ground, Body effect exists RI is the resistance from previous stage
J. Schwartz, 2007 FETs 5.2.48 Page 24 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CDA
• Replace with a “real” current source including output resistance ro2 • No problem including AC CLM (since drain is at signal ground)
Two types of analysis: Neglect AC BodyEffect
Use AC BodyEffect
J. Schwartz, 2007 FETs 5.2.49 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CDA Without Body Effect AV =
iG=0 ro 2 ro1 vo = vI ro 2 ro1 + g1 1 m
RIN ⇒ ∞
ROUT = ro1 ro 2
1 g m1 J. Schwartz, 2007 FETs 5.2.50 Page 25 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CDA With Body Effect J. Schwartz, 2007 FETs 5.2.51 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CDA With Body Effect v gs1 = vI − vo
vo = (g m1v gs1 ) ro 2 ro1 ( = g m1 (v I − vo ) ro 2 ro1 ( 1 g mb1 )
1 g mb1 ) RIN ⇒ ∞
J. Schwartz, 2007 ro 2 ro1 g mb1 vo = 1 vI ro 2 ro1 g mb1 + ( ( 1 ) )
1 g m1
FETs 5.2.52 Page 26 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CDA With Body Effect  ROUT
Short input voltage source IX VX v x = (g m1v gs1 + ix ) ro 2 ro1
ROUT v gs1 = −v x ( 1 g mb1 )
) 1 ro 2 ro1 g mb1 vx == 1 ix 1 + g m1 ro 2 ro1 g mb1 ( By sourceabsorption:
ROUT = ro1 // ro 2 //(1 / g m1 ) //(1 / g mb1 )
J. Schwartz, 2007 FETs 5.2.53 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Combined Bipolar & CMOS: BiCMOS
• Mix of BJT’s and MOSFETs in same IC process • With this enhanced technology, we can take advantage of: – The large gain of the BJT (gm) – The infinite input gate resistance of the MOSFET • Also in the digitaldomain: – The CMOS to do the very dense logic processing – The bipolar to drive the onoff chip signals with more current and matched 50Ω impedance J. Schwartz, 2007 FETs 5.2.54 Page 27 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Example: CSA
• MOSFET CSA – No loading at input from RG – Found gain to be: vo = − g m1 (ro1  ro 2 ) vS
• However, the gain limited by MOSFET gm • It can be improved using BJT’s
J. Schwartz, 2007 FETs 5.2.55 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics MOSFETBJT Amplifier
Neglect all ro’s except current mirror  CGA (r03 from current mirror): vo = − g m1ro 3v gs1 v x = −v gs1 vo = v x g m1ro 3
 CGA input resistance: RIN = 1 / g m1 RIN  CEA: v x = − g m 2 RIN vbe 2
rπ vS RS + rπ
vx g rπ = − m2 vS g m1 RS + rπ vbe 2 = vo vo v x r = = − g m 2 ro3 ⋅ π vS v x vS rπ + RS
J. Schwartz, 2007 FETs 5.2.56 Page 28 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Outline of Section 5
• • • • • • • • • 5.1 Intro to MOS Field Effect Transistor (MOSFET) 5.2 NMOS FET 5.3 PMOS FET 5.4 DC Analysis of MOSFET Circuits 5.5 MOSFET Amplifier 5.6 MOSFET Small Signal Model 5.7 MOSFET Integrated Circuits 5.8 CSA, CGA, CDA 5.9 CMOS Inverter & MOS Digital Logic J. Schwartz, 2007 FETs 5.2.57 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CMOS Inverter
• MOSFETs can act as almost ideal current switches with symmetric VTCs and railtorail logic. • Matching of MP and MN: VtP = VtN = Vt • Since typically k’P is 23 times smaller than k’n, the widths of the transistors are used to compensate:
WP = 3WN
k′ p W WP ′ = kn N LP LN VI • This is definition of matched devices; equal current driving and sinking capabilities when charging & discharging capacitive loads
J. Schwartz, 2007 FETs 5.2.58 Page 29 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics CMOS Inverter – Operation
ON! VGS(p)>Vtp VGS(p)<Vtp VGS(n)>Vtn ON! nMOS transistor pulls output voltage to the most negative rail. VGS(n)<Vtn pMOS transistor pulls output voltage to the most positive rail.
FETs 5.2.59 J. Schwartz, 2007 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Inverter VTC
• Region I: VIN < Vt
I II III IV V – MN cutoff, MP in triode – Lowresistance path from VDD to VOUT pulls output high – No current flow • Region II: VIN > Vt
– MN enters saturation – MP still in triode – Current flows, VOUT starts to fall VOUT • Region III:
VIN
– Highgain region – MN & MP saturated – VTC slope = gain
FETs 5.2.60 J. Schwartz, 2007 Page 30 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Inverter VTC
• Region IV:
I II III IV V – MN enters triode – MP still in saturation • Region V: VIN > VDDVt
– MP cutoff, MN in triode – Lowresistance path from VOUT to ground pulls output low – No current flow VOUT J. Schwartz, 2007 VIN FETs 5.2.61 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics VTC Characteristics
VOH=5V • A matched inverter has symmetric voltage transfer characteristic. • VOL and VOH are defined as 0V and 5V respectively. • VIH and VIL defined as location where VTC slope = 1
– VIL is in region II – VIH is in region IV
FETs 5.2.62 VOL=0V
J. Schwartz, 2007 Page 31 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Finding VIH – Matched Devices
• In region IV, MP saturated, MN in triode:
′ kn 1 2 ⎤ 1 WP WN ⎡ 2 p ⎢(VIN − Vt )VOUT − 2 VOUT ⎥ = 2 k ′ L (VIN − VDD + Vt ) LN ⎣ ⎦ P
2 (VIN − Vt )VOUT − 1 VOUT 2 = 1 (VIN − VDD + Vt )2 2 1 • VIN = VIH when
VOUT + (VIN − Vt ) ∂VOUT = −1 ∂VIN ∴ Take derivative wrt VIN ∂VOUT ∂V − VOUT OUT = (VIN − VDD + Vt ) ∂VIN ∂VIN
VDD 2 • Substitute VIN = VIH & simplify to get: VOUT = VIH −
J. Schwartz, 2007 FETs 5.2.63 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Finding VIH – Matched Devices
• Take result for VOUT when VIN = VIH
VOUT = VIH − VDD 2
2 • Substitute into 1 (VIH − Vt )⎛VIH − VDD ⎞ − 1 ⎛VIH − VDD ⎞ ⎟ ⎜ ⎟ ⎜
⎝ 2 ⎠ 2⎝ 2⎠
8 = 1 (VIH − VDD + Vt )2 2 • Solving for VIH, get: VIH = 1 (5VDD − 2Vt ) J. Schwartz, 2007 FETs 5.2.64 Page 32 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Finding VIL – Matched Devices
• Can use similar procedure to find VIL
– Write equations for region II operation:MP in triode, MN in saturation – Solve for VOUT when VIN = VIL and substitute back into equations and solve for VIL • Result: • Alternatively, can find VIL using symmetry of VTC because VIL and VIH are symmetric about VDD/2
VIH −
J. Schwartz, 2007 VIL = 1 (3VDD + 2Vt ) 8 VDD VDD = − VIL 2 2
FETs 5.2.65 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Noise Margins
NML, Low Noise Margin Definition: NM L = VOH − VIH = VDD − VIH
NM L = VOH − VIH = VIH = 1 (3VDD + 2Vt ) 8 1 (5VDD − 2Vt ) 8 NMH: High Noise Margin Definition: NM H = VIL − VOL = VIL − 0
NM H = VIL − VOL =
J. Schwartz, 2007 VIL = 1 (3VDD + 2Vt ) 8 1 (3VDD + 2Vt ) 8
FETs 5.2.66 Conclusion: NMs equal for matched devices Page 33 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Mismatched Inverter Characteristics
• For mismatched devices: Vtp ≠ Vtn k′ p W WP ′ ≠ kn N LP LN • VTC not symmetric any longer • VIL and VIH can be found using same approach as before, with more algebra • Resulting VTC noise margins will not be equal, but VOH and VOL will be unchanged
J. Schwartz, 2007 FETs 5.2.67 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Structure of CMOS LogicGates
• PUN: pullup network (PMOS transistors) • PDN: pulldown network (NMOS transistors) • PUN & PDN almost invariably made complementary networks
– i.e. seriesconnected transistors in one network are parallelconnected in the other & vice versa – Facilitates formal design and logic synthesis techniques
FETs 5.2.68 PullUp Network PullDown Network J. Schwartz, 2007 Page 34 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Basic PullUp Structures Parallel Structure VOUT is high when either VA or VB is low Serial Structure VOUT is high when both VA and VB are low VOUT = V A + VB
J. Schwartz, 2007 VOUT = V A ⋅ VB
FETs 5.2.69 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics Basic PullDown Structures Parallel Structure VOUT is low when either VA or VB is high Serial Structure VOUT is low when both VA and VB are high VOUT = V A + VB
J. Schwartz, 2007 VOUT = V A ⋅ VB
FETs 5.2.70 Page 35 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics 2Input CMOS NAND Gate
Truth table:
PUN: VOUT = V A + VB VOUT = V A ⋅ VB PDN: Logic Symbol: VOUT = V A ⋅ VB J. Schwartz, 2007 FETs 5.2.71 Department of Electrical and Computer Engineering ECSE330 Introduction to Electronics 2Input CMOS NOR Gate
Truth table:
PUN: VOUT = V A ⋅ VB VOUT = V A + VB PDN: Logic Symbol: VOUT = V A + VB J. Schwartz, 2007 FETs 5.2.72 Page 36 ...
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