c - EEiL3701 — Dr. Gugel Last Name Spring 2009 « Final...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 2
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 4
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 6
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: EEiL3701 — Dr. Gugel Last Name Spring 2009 « Final Quiz UF iD# First Name k ‘E s - Open book and open notes, 90-minute examination to be done in pencil. 0 No electronic devices are permitted. ° All work and solutions are to be written on the exam where appropriate. Point System (for instructor and TA use only) Page 2) Page 3) Page 4) Page 5) Page 6) TOTAL Grade Review information: (NOTE: deadline of request for grade review is the day the exam is returned.) 10 points 12 points 10 points 4 points 14 points out of 50 1. A vector containing signed (2’s complement) 8 bit numbers is stored in memory. Write a program using G-CPU v instructions that separates the elements of this vector into two separate vectors where one contains only positive numbers and the other contains only negative numbers. (10 pts.) Assume the following: The length of the original vector is an 8 bit unsigned number stored at address $1000 and is less than 80 Hex. The starting address of the original vector is stored at addresses $1001 and $1002. The starting vector address for the separated positive numbers should be equal to $1100. The starting vector address for the separated negative numbers should be equal to $1180. Zero can be treated as a positive number. Use the X register as a pointer to the original vector. Use the Y register as a pointer to store the positive & negative vectors. 9. Use the B register as your counter. Assume you also have the following commands available: DECB, DECA and that the flags are set by either the A or B register contents. h. End your program in an infinite loop. finance Write your answer on the leftmost column lines and then if you need more room wrap around to the rightmost column. ORG $0 4'1)wa /Ool LL“ 1% m5. l. l______________________ LOW/5 ‘3 $1600396f/enjfio ,_mw——__ BPJ IVEG Eckdi3 mg I l M“ ‘— i fifthv'e 5W ?l DECB i count“: COL/Maj") l ENE 76,0 41.5 ‘ Dome 15.5432. Doug 0.5 Page 2 Page Score = 2. Given the following ASM Diagram, design circuits for the outputs in the ASM. Use D Flip-Flops and the design with “ NAND gates only. Assume Z.H, A.L, B.L and C.L. State variables are Q1 .H (M88) and QO.H (LSB). Derive the MSOP Logic Equations for D1 and D0. Derive circuits for A.L, B.L and C.L using 3-input NAND gates. Show all work below. (12 pts.) D\ De Logic Equations in MSOP Form: D—FF input D1 (MSB) = D-FF input D0 (LSB) = C.L w.t..KW.v_.vM.a_._..,.._t..~‘t.m._... 3. In lab #9 we were only able to place opcodes/operands (assembly instructions) into 16 possible memory locations of the 32K x 8 ROM. instead we would like to be able to program up to 256 different memory locations with instructions. Describe the required hardware modifications required to perform this and be as specific as possible for maximum credit. (2 pt.) Ckwjfl; pc {Imam iLO 35+; W736 4. In lab #9, if we wanted to increase the number of instructions in the CPU instruction set, what hardware modifications are necessary? Assume that many of the new instructions will also require new states in the controller ASM. (2 pt.) 2' Morng SIZE Ilfl. Wow: F/F; o cofiryallev 5:14:7in 57am; 1,; MM 5. In lab #9, if the CPU now has an 8 bit input (data) bus, what hardware modifications are necessary in the CPU? (2 pt.) Re 5. Awarewglg MWMmW-g mi 41.1% ,4? I? bwf a“ Obit low; :‘5 Y3] MKXQ 7Q, MU“ 6. Upon changing the hardware required above in #3, we now can add an extended addressing mode for the LDAA instruction. i.e. LDAA addr; where address is an 8 bit operand. Assume we still have a 4 bit input( ((91%) bus. Draw the new hardware required and also list the new controller outputs required for this new instruction. (4 pt.) M [242/ LD; L 7. For the previous problem, assume we will use opcode 101 in the controller ASM for the new LDAA Addr instruction. Show the required conditional outputs and/or states below for this instruction in the ASM. (4 pt.) TAB LDAA #data SAR 000 001 010 ABA SAL LDAAAddr JMPAddr 011 100 101 111 Fill in the required items for the LDAA Addr instruction only. Show all Controller outputs that are true in this path. i.e. MSA1 :0, MSB1:0, M8020, etc. Upon completing this instruction, show where the flow returns to begin execution of a new instruction. x g i i l a . Page 5 Page Score = 8. The G-CPU program below was put in EPROM starting at address $00F0; answer the questions that follow. LDX #$1oo1 0,1,2, LDAA #$3 STAA $1OFF 2’” 6,423)? 0 F8 T1 LDAA o,x 1‘ A o TAB m 31" K s@ SHFA_L f 7L D SHFA_L , M a); SUM_BA D Map 3 Q STAA $80,X INX LDAA ¥$1OFF LDAB #$FF ADD_BA STAA $10FF BNE T1 T2 BEQ T2 8A. SRAM initially contains the following data before program execution: $1000[OO], $1001[01], $1OFF[FF]. After program execution what SRAM data has been modified? Show the modified addresses and corresponding data below. Show modified SRAM memory in hex in the following format: Addr [data] (4 pt.) I'm-(1095)) (“2123247) {0836316) ) [0121100] 8B. In the last execution of the loop, what is the effective address for the STAA $80,X instruction? (1 pt.) [0?3 80. What is the effective address for the LDAA #$3 instruction? (1 pt.) 00:4 8D. Fill in the EPROM program contents (data values) in hex (2 pt.): Address (Hex) Data (Hex) ’ 00F8 oo FD 04 3 OCH; g 3;; 00 fig [16] OOFA @ 00 . . OOFB i Q 00 Pp [‘20] 99) 8E. Show the expected values for each of the column variables below for all the cycles required to execute the SUM_BA and STAA $80,X instructions the first time they are executed. All answers in Hex. (6 pt.) Note: All Columns Below Should Have at Least One Known Value! Device Device Driving Driving Addr Bus Data Bus Cycle Addr Bus Data Bus E E Rl-W XReg RegA Reg B pc, flora/L o4 0' Ill mFD / [bol 1 $OOFD M 2 ODFD l4 Wflflg—pfla 3 OOFE: [G [Ll 0013?: l 1001 05 0’ fa K “M 00% l 160‘ 0:; 0 I ,m mm 4 00% gt: 1: ME I we: 65 01 pc 12mm 5 or??? I o 05 m ,Xglmk GCP/itfluw 6 0‘5 [0 OlOO O l0 l (flea/firksbdza ...
View Full Document

Page1 / 6

c - EEiL3701 — Dr. Gugel Last Name Spring 2009 « Final...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online