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# b - EEL3701 — Dr Gugel NAME k E 2 Spring 2008 Exam ll UF...

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Unformatted text preview: EEL3701 — Dr. Gugel NAME k E 2 Spring 2008 Exam ll UF ID# - Open book and open notes, 90-minute examination to be done in pencil. : 0 No electronic devices are permitted. - All work and solutions are to be written on the exam where appropriate. Point System (for instructor and TA use only) :3 W‘ Page 2) 12 points ’f Page 3) 16 points 1 ”V Page 4) 16 points Z- Page 5) 10 points E 3' Page 6) 24 points Page 7) No points g Page 8) 22 points 3 TOTAL out of 100 Grade Review information: (NOTE: deadline of request for grade review is the day the exam is returned.) Part I. Flip Flop Creation. Using the JK Flip-Flop shown below and any logic gate (ANDs, ORs, lNVERTERs, etc.), create a G Flip-Flop with a SYNCHRONOUS set. Assume all inputs & outputs are high true, J Q . . +lo lC G Given: ELK /Q 9 Design this: SET /QQ Page Score = Part II. State Machine Design. Design an Up CoUnter with one input named Even/Odd (E0. H) such that when EO= H count 0,2, repeat and when EO= L count 1 ,3 repeat. EO. H Is an asynchronous input and if it is changed from H to L during operation, the counter should go to the nearest odd number counting up. Similarly if E0 is changed from L to H during operation, the count should go to the next even number counting up. in addition to the counter outputs you should also have two outputs X.L and Y.L as specified: X.L = true, if the present state is odd. Y.L = true, if the present state is even AND EO.H = true. 2. Assuming EO.H, X.L, Y.L, draw the Mealy Logic Diagram for the design. (8 pt.) EosH Con/0i (9)90.” 3. Complete the first four lines of the logic next state table below. (8 pt.) Page Score = ,. 2 l l l l l l l I l g i x S i l l l l r I E 4. If we decide to implement the state machine using T Flip-Flops, draw the functional block diagram for the system below. Show all flip-flops, inputs and outputs. (6 pt.) 3 (32+ Hold 1 /Q X 40?le 5. What is the Min. Product Of Sum (MPOS) logic equation for the T input for the most significant counter flip- flop? Show all work for partial credit purposes. Label the next state table as shown in #3 earlier. (6 pt.) 6. What is the MPOS logic equation for X.L? (4 pt.) Page 4 Page Score = i l .. § 5 S t t . E l E i' l s l I t; 7‘. Draw the circuit for Y.L assuming a Min. Sum of Products (MSOP) solution. (6 pt.) Part Ill. Next State Tables, ASM Diagrams & ROM Implementations. Given the following Next State Logic Table and signal definitions, answer the questions that follow. A Emu-- Qo+ Inputs = A.H Outputs = Y.L, Z.H State Variables = Q2, Q1, 00 8. In what states are Y and Z unconditional outputs only? (4 pt.) 5mm 3 :7 ﬂ 1'6 02 I? 997% 6/”ng 7/ 5? ”)2; Page Score = Page 5 MMKMWW_~W:UW.‘,4TI I: . 9. For the previous Next State Table, draw the corresponding ASM Logic Diagram. (12 pt.) 10. If we implement the state machine in the EPROM below and three D Flip-ﬂops, what should the address and memory contents be for the lines in the next state table when A = 0 (false)? (10 pt.) +5V No Connect : E: 82:12:: Ql-H Big Q0.H D0.H l/ lul/llll >009 11. How many Kilo-bytes does this EPROM contain? (2 pt.) Page Score = Part IV. ASMs, Synchronous & Asynchronous Signals, Timing Diagram You are given two Flip-flops connected as shown below. An Algorithmic State Machine is used to control the Flip—flop clear signals via Synchronous CLR1.H and Asynchronous CLRO.H. GND GND +5V OUT.H CLK CLR1.H (Synchronous) CLRO.H (Asynchronous) ASM Controller Logic Diagram ASM Controller X.H Y.H i r E l i g i E. 2 5 l E 3 gr 5 l l i r CLK MM..rw..‘_MW-TW.._.W.M«M.VT_MW...“n..n‘u_....l.wr...<m__mm.M". Page 7 Page Score = 12. Complete the following Logic Timing Diagram for all signals shown below. (16 pt.) ,5 Fill out Signals for STATE 33% so 5 s l s 67/ 50 ’9 State, CLRl, CLRO ._ Q1 AND OUT! T ' . i ' E CLRl g 5 ‘ g g CLRO E i 3 i i F T Q1 OUT 3 l g 14. Create a 2 bit register below that contains a synchronous load (—LD) input and outputs that can be tri-stated via an output enable signal (-OE). You may use any device available and are not allowed to have a gated clock in your design. Assume it is a rising edge triggered device. v (6 pt.) 08 2 Bit Register [N1 :0 OUTl :0 CLK -LD -OE . \}_ .. lel PAUWK g page 8 ' 54 ’ Page Score = l ...
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b - EEL3701 — Dr Gugel NAME k E 2 Spring 2008 Exam ll UF...

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