16 - 5-Oct-102:04 PM RAM, ROM EEL 3701 EEL 3701 Menu LSI...

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5-Oct-10—2:04 PM RAM, ROM 1 University of Florida, EEL 3701 – File 16 © Drs. Schwartz & Arroyo EEL 3701 EEL 3701 Menu •LSI Components >Random Access Memory (RAM) – Static RAM (SRAM) – Dynamic RAM (DRAM) – Read-Only Memory (ROM) Look into my . .. 1 University of Florida, EEL 3701 – File 16 © Drs. Schwartz & Arroyo See figures from Lam text on web: RAM_ROM_ch6.pdf EEL 3701 EEL 3701 • It can be thought of as 1 long vector of registers . Each register is given the “name” of its ordered index or location. We call this the dd Add ll i i HEX Static Random Access Memory(SRAM) address . Addresses are usually given in HEX. [Example] 1 k x 8 RAM word size 000 001 002 0 1 2 . . Location or # of words 70 1K = 1024 bytes = 2 10 byte 2 University of Florida, EEL 3701 – File 16 © Drs. Schwartz & Arroyo 3FD 3FE 3FF HEX . 1021 1022 1023 Decimal “Address” 1 byte = 8 bits bytes • 8 bits = 1 byte, 4 bits = 1 nibble, • 1k = 2 10 =1024, M=2 20 (mega-), G=2 30 (giga-), T=2 40 (tera-) • 1k x 8bits = 1KB = 1 kilobyte = 2^10 bytes
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5-Oct-10—2:04 PM RAM, ROM 2 University of Florida, EEL 3701 – File 16 © Drs. Schwartz & Arroyo EEL 3701 EEL 3701 •To address 1k = 2 10 bits, we need 10 “address lines” (A 9 ~A 0 ) •The data needs 8 lines designated as D 7 ~D 0 •Since any of the 1k locations is usable the address lines Static RAM Postfix Abbr : H = Hexadecimal, B = Binary, O = Octal, and D = Decimal Since any of the 1k locations is usable, the address lines A 9 ~A 0 will range from 00 0000 0000B to 11 1111 1111B ( 0 0 0H) to ( 3 F FH) • Any RAM chip will have n Any RAM chip will have n-address lines, m address lines, m-data lines, and a “few” data lines, and a “few” 3 University of Florida, EEL 3701 – File 16 © Drs. Schwartz & Arroyo control lines. • For RAM, “control” is usually a CE or CS (Chip Enable or Chip For RAM, “control” is usually a CE or CS (Chip Enable or Chip Select), a WE (Write Enable), a RD (Read) or OE (Output enable), etc. • The data lines are usually bi The data lines are usually bi-directional (time directional (time-multiplexed). multiplexed). • To “save” pins, WE may indicate the direction of data travel. To “save” pins, WE may indicate the direction of data travel. Prefix Abbr : $ = Hexadecimal, % = Binary, @ = Octal EEL 3701 EEL 3701 (Static) RAM Model • RAM's are said to be volatile ,” i.e. ., information CS/CE,WE, . .. A n-1 ~ A 0 n D m-1 ~ D 0 m Data Bus Address Bus remains while power is “on.” • Typical access times for SRAM are 10 ~ 100ns in CMOS types. Faster (less capacity in bytes) IC technology (TTL, etc.) are See Lam Fig 6.21 - 6.25 (show!) A 9 ~ A 0 10 Control Bus Operation CE WE D Disable 0 H Z 4 University of Florida, EEL 3701 – File 16 © Drs. Schwartz & Arroyo also available.
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This note was uploaded on 01/06/2011 for the course EEL 3701c taught by Professor Gugel during the Spring '05 term at University of Florida.

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16 - 5-Oct-102:04 PM RAM, ROM EEL 3701 EEL 3701 Menu LSI...

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