GCPU_Block_Instr - 15,5 1.3 5.3,...fi. ,..._.F,,..;,\‘

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 2
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 4
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 15,5 1.3 5.3,...fi. ,..._.F,,..;,\‘ “154.2,.ffififf. V. $94..” f LS .,_ 2%Eunififééflgfiwfifivaggavfiiazfiifitfifw . ,. 3:5.xfifihégxawanEnuguaneififlfiinjiac.\f; miiue; :h.;p.v,;.z.¥§a 9.55.5.) : AMPS mom > + mom #58033me > H Moofim mom > SF: mom N + mom Eofioomfimmv N M £85 mom N £5 2 2m 3:350 > “N “#364 “DA 682 on Smmlmmnz om Hm #85 Mom > #85 mg x 3%: fix e? :52 mm?flm~émxm&w m N _ 0 x32 Awsd 5:500 :53on 25 8333‘ 3d,» 318m 93% man? a? n: E SSW 51> 07: > 35V 51x 05% mg 2 3551322 calm/*2 mam N 351v 5 um 07: 0m ‘4 “MM-M mm » , ‘ mwzm, a - 533% v50 :5: SIM: o W 3:95.80 m 9| mam San. Raouoobw¢m W 7?. a; En.qu323,1“Efiflnguuufiévggyéngn£2.h 3.fiiuflzx35%“:mgfikpfikuggééfigfigfluggfi“in 32%.GEEKEEkn5i n,gififigfizénéfifiufifig , gmfigéfifiigfizfifigfifiprfig3k.e?£c§wfic{45.52 ,52y,HuEggiuagggfiihgasgg $2.12:an 3an 8 26 :32? «a: “33: ngfin v.35 DmU U 1 :0 F mme 259w 95am Taiwoawwnvhflfln . 3:5; “.115 V x382 aura.“qu x :ozflmcmo mmE z w N m Emumz Emaxmuzm o S _ cfiumuzm w c o v Emilfizm o o o w =31<u1m p w _‘ a £80 a F V o <28 r o w a 34.76 a o w a S.<Ez¢ r E a 5.35% o _ o a mama .v o o o < Emomz 60%; ,L 30mm Bow: 2cm”? 53.....35 i 1:30 , figm u 5.: ESQEoo “wow—oi :5.23238389383FEQamREmBB.c=.__:s $5;ng x85 m 3m .< mg .m 5:2 .< .92 meow .mv BnEw>oZ H9mm. ELEXXi..3.:i.i'|‘\‘ :1 University of Florida EEL 3701 Department of Electrical & Computer Engineering Revision 0 Page 1/2 G—CPU Instruction Set Drs. Gugel and Schwartz Professors in ECE 19-Nov—02—2257 PM # of Description States Transfer A to B (inherent addressing) Transfer B to A (inherent addressing) LDAA #data 8 bit data Load A with immediate data (immediate addr.) 8 bit data 16 bit address Load A with data from memory location addr (extended addressin) 5 LDAB addr 16 bit address Load B with data from memory location addr 5 -- I I 16 bit address Store data in A to memory location addr (extended addressing) 7 STAB addr 16 bit address Store data in B to memory location addr (extended 5 -- I I.— _ Data Movement Instructions: _ none - none - - Operand LDX #data 16 bit data Load X with immediate data (immediate addr.) LDY #data 16 bit data Load Y with immediate data (immediate addr.) A LDX addr 16 bit addr Load X with data from memory location addr.- (extended addressing) LDY addr 16 bit addr Load Y with data from memory location addr. (extended addressing) LDAA dd X 8 bit Load A with data from memory location pointed to 4 dis lacement by X + dd (indexed addressing) LDAA dd Y 8 bit Load A with data from memory location pointed to 4 dis lacement by Y + dd (indexed addressing) LDAB dd X 8 bit Load B with data from memory location pointed to 4 dis p lacement by X + dd (indexed addressin) 8 bit Store data in A to memory location pointed to by X dis lacement + dd (indexed addressing) ' STAA dd,Y 8 bit Store data in A to memory location pointed to by Y STAB dd,X 8 bit Store data in B to memory location pointed to by X+ LDAB dd Y 8 bit Load B with data from memory location pointed to dis lacement by Y + dd (indexed addressing) 8 bit Store data in B to memory location pointed to by Y + dis lacement dd (indexed addressing) l l i if i i. l s University of Florida EEL 3701 Department of Electrical & Computer Engineering Revision 0 Drs. Gugel and Schwartz Professors in ECE Page 2/2 G—CPU Instruction Set 19-Nov—02—2z57 PM ALU Related Instructions: 14 || 30 ncrement X (inherent addressing) 31 _ SUM_BA Shift B right by one bit (inherent addressing) none ncrement Y inherent addressin Opcode I3- Special Notes 1. Z flag and N ag are only set and cleared by the contents in register A. 2. A branch is accomplished by moving the operand address “addr” to the lower byte of the PC. The upper byte of the PC remains unchanged after a branch. 3. The Branch Instructions use absolute addressing where only the low byte of the address is used as an operand. If the branch condition is met, the high byte of the PC is unchanged and the low byte takes the value of the operand (ader). ...
View Full Document

Page1 / 4

GCPU_Block_Instr - 15,5 1.3 5.3,...fi. ,..._.F,,..;,\‘

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online