Tutorial Set 1C

# Tutorial Set 1C - EE2006: Digital Design 15. Design a...

This preview shows pages 1–2. Sign up to view the full content.

EE2006: Digital Design 3 15. Design a circuit to realize D B D C B B A Z in the positive logic convention. A and B are active low signals while C , D and Z are active high. Use a minimum number of gates, and draw clear circuit diagrams with alternate gate representations as required. Assume that only 74’00, 74’02, 74’04, 74’10, and 74’27 chips are available. 16. A combinational circuit has four inputs A, B, C and D and an output Z. The output is 1 whenever three or more of the inputs are 1, otherwise the output is 0. Find a) an MPOS expression and b) an MSOP expression for Z. Design combinational circuits for the two expressions using only 74’04 inverters, 74’00 2-input NAND gates and 74’10 3-input NAND gates. Assume that A, B and Z are active high signals, while C and D are active low signals. Use alternate gate representations for clarity of circuit diagrams. Combinational MSI circuits

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

## This note was uploaded on 01/08/2011 for the course EE 2006 taught by Professor Dr. during the Spring '10 term at National University of Singapore.

### Page1 / 3

Tutorial Set 1C - EE2006: Digital Design 15. Design a...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online