Lecture 5 8405 - CH 6 - PIPELINING INTRODUCTION - basics of...

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CH 6 - PIPELINING INTRODUCTION - basics of pipelining and the problems that are generated by this technique. Basic Principle is simple: Divide up the instruction execution into discrete parts, much like the multicycle processor: IF - Instruction fetch ID - Register read/ Instruction decode EXE - Execute operation MEM - Memory Access WB - Write back Note that all instructions will write back on the 5th cycle (normally); data will remain on hold during mem access stage if there is no mem access. Key: can execute several instructions in parallel- up to five- because we have five 'functional units' in our pipeline. If instruction n is being executed, n+1 is doing register read, n+2 is being fetched, n-1 is being memory accessed, and n-2 being written back. How does this improve performance? Before, each instruction would have taken 5 cycles. Now, a new instruction might be fetched every cycle- giving an upper-limit performance increase of: MaxSpeedup = CyclesBefore/EffectiveCyclesAfter = pipelineStages It looks as if each instruct takes one cycle! However, execution for a given instruction is the same, or more (due to delayed writeback), than for multicycle. Let's look at an example: ClockCycle: 1 2 3 4 5 6 7 8 9 10 add $2,$3,$4 if id exe mem wb lw $4,0($2) if id exe mem wb beq $4,$0,foo if id exe mem wb sw $2,0($6) if id exe mem wb Much better, right? Well, yes and no. There are a few problems. HAZARDS are situations where the result of an instruction must be determined in order to be able to execute later instructions. 1
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There are three basic types of hazards: 1) Structural hazards occur when the hardware is incapable of supporting the operations needed in the same clock cycle. MIPS is so simple that it does not have structural hazards. If, however, program and data memory were unified, then mem read could not be done at the same time as IF. Or, if there were a two-cycle divide unit that was not pipelined, couldn't have adjacent divide instructions. Solution: STALL. Continue the earlier instruction's execution, but hold back all later instructions one cycle so the conflict can be resolved. This inserts a BUBBLE into the pipeline where useful work is not being done. 2) Control hazards occur because until a conditional branch is evaluated, or a jump address determined, the address of the next instruction is unclear. Question: in the example above, when is the address of the instruction after the branch available? (After bra exe, could do sw if). Solutions: a) Stall until decision known (2 clocks IF branch calculated early) b) Assume "branch-not-taken" and inhibit WB if branch c) Assume "branch-taken", which causes at least one stall d) Branch prediction: keep track of each branch address and whether the last three times branch was taken or not more often. *** Prediction is used in most systems. NO STALLS unless wrong. e) Delayed branch. The instruction after the bra is assumed to always
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Lecture 5 8405 - CH 6 - PIPELINING INTRODUCTION - basics of...

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