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# lec11 - CS 140 Lecture 11 Sequential Networks: Timing and...

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CS 140 Lecture 11 Sequential Networks: Timing and Retiming Professor CK Cheng CSE Dept. UC San Diego 1

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Sequential Networks Timing: Setup Time and Hold Time Constraints D Q Q’ CLK 2
Combinational CLK CLK A B C A typical sequential network has both a combinational circuit and flip-flips. D Sequential Networks 3

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Combinational CLK CLK A B C t cq + t comb + t setup < T t hold < t cq + t comb Clock period Shortest path 4
Input Timing Constraints • Setup time: t setup = time before the clock edge that data must be stable (i.e. not changing) • Hold time: t hold = time after the clock edge that data must be stable • Aperture time: t a = time around clock edge that data must be stable ( t a = t setup + t hold ) CLK t setup D t hold t a 5

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• Propagation delay: t pcq = time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing) • Contamination delay: t ccq = time after clock edge that Q might be unstable (i.e., start changing) CLK t ccq t pcq Q 6
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## This note was uploaded on 01/07/2011 for the course CSE 140 taught by Professor Rosing during the Spring '06 term at UCSD.

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lec11 - CS 140 Lecture 11 Sequential Networks: Timing and...

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