# lec9 - CSE 140 Lecture 9 Sequential Networks Professor CK...

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1 CSE 140 Lecture 9 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego

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2 Combinational CLK CLK A B C D Sequential Networks 1. Components F-Fs 2. Specification 3. Implementation: Excitation Table
3 Specification Finite State Machine: Input Output Relation State Diagram State Table Circuit: Logic Diagram Netlist Boolean Expression

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4 Netlist State Table State Diagram Input Output Relation y(t) = Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)Q 1 (t) Q 1 (t+1) = D 1 (t) = x(t) + Q 0 (t) x Q 0 Q 1 D Q Q’ D Q Q’ y Q 1 Q 0 D 1 D 0 Clk
5 Netlist State Table State Diagram Input Output Relation x Q 0 Q 1 D Q Q’ D Q Q’ y Q 1 Q 0 D 1 D 0 y(t) = Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)Q 1 (t) Q 1 (t+1) = D 1 (t) = x(t) + Q 0 (t) Clk

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6 State table 0 0 0 1 1 0 1 1 PS input x=0 x=1 0 0 , 0 1 0 , 0 1 0 , 0 1 0 , 0 0 0 , 0 1 1 , 0 1 0 , 1 1 1 , 1 Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1), y(t) S 0 S 1 S 2 S 3 PS input x=0 x=1 S 0 , 0 S 2 , 0 S 2 , 0 S 2 , 0 S 0 , 0 S 3 , 0 S 2 , 1 S 3 , 1 Let: S 0 = 00 S 1 = 01 S 2 = 10 S 3 = 11 Remake the state table using symbols instead of binary code , e.g. ’00’ y(t) = Q 1 (t) Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t) Q 1 (t) Q 1 (t+1) = D 1 (t) = x(t) + Q 0 (t) Logic Diagram => State Table
7 State Table => State Diagram Example: Output sequence S 0 S 1 S 2 S 3 PS input x=0 x=1 S 0 , 0

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## This note was uploaded on 01/07/2011 for the course CSE 140 taught by Professor Rosing during the Spring '06 term at UCSD.

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lec9 - CSE 140 Lecture 9 Sequential Networks Professor CK...

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