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# lec8 - CSE 140 Lecture 8 Sequential Networks Professor CK...

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CSE 140 Lecture 8 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego 1

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Part II. Sequential Networks (Ch. 3) Memory / Time steps Clock Memory: Flip flops Specification: Finite State Machines Implementation: Excitation Tables x i y i s i y i =f i (S t ,X) s i t+1 =g i (S t ,X) 2
Memory Devices Memory Storage Latches Flip-Flops SR, D, T, JK State Tables Characteristic Expressions 3

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Memory Storage: Capacitive Loads Fundamental building block of other state elements Two outputs: Q , Q No inputs Q Q Q Q I1 I2 I2 I1 4
Capacitive Loads Q Q I1 I2 0 1 1 0 Consider the two possible cases: Q = 0: then Q’ = 1 and Q = 0 (consistent) Q = 1: then Q ’ = 0 and Q = 1 (consistent) Bistable circuit stores 1 bit of state in the state variable, Q (or Q’ ) But there are no inputs to control the state Q Q I1 I2 1 0 0 1 5

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SR (Set/Reset) Latch R S Q Q N1 N2 SR Latch Consider the four possible cases: S = 1, R = 0 S = 0, R = 1 S = 0, R = 0 S = 1, R = 1 6
SR Latch Analysis S = 1, R = 0: then Q = 1 and Q = 0 S = 0, R = 1: then Q = 0 and Q = 1 R S Q Q N1 N2 0 1 R S Q Q N1 N2 1 0 7

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SR Latch Analysis S = 1, R = 0: then Q = 1 and Q = 0 S = 0, R = 1: then Q = 0 and Q = 1 R S Q Q N1 N2 0 1 1 0 1 0 R S Q Q N1 N2 1 0 0 1 0 1 8
SR Latch Analysis

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lec8 - CSE 140 Lecture 8 Sequential Networks Professor CK...

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