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Unformatted text preview: ECE102Fall 2010 Project – Op Amp Design Design a differential input/output operational amplifier based on the topology shown. This is a two ‐ stage design. The first stage is a differential pair with current source loads while the second stage is a pair of common source designs. A common ‐ mode feedback loop (shown as shaded circuitry) is included to help set the bias properly. First set the dc bias and transistor conditions such that all the devices are in saturation when V IN+ =V IN ‐ =1.25V. The output common ‐ mode voltage V CM =1.25V (with V OUT+ =V OUT ‐ =1.25V). The supply voltage V DD =2.5V, the reference current I REF at 5uA, and the total power dissipation must be less than 150uW. Verify that the low ‐ frequency small ‐ signal differential voltage gain equals 40dB or more. This may require re ‐ sizing some transistors. In general, the gain of the op amp can be increased by increasing the W/L ratio of the gain transistors or by decreasing the W/L ratio of the current...
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This note was uploaded on 01/08/2011 for the course ECE 102 taught by Professor Gilman during the Fall '08 term at UCSD.
- Fall '08