hw4 - 0.5 . Set the device sizes of M 1 through M 8 and the...

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UNIVERSITY OF CALIFORNIA, SAN DIEGO Department of Electrical and Computer Engineering Bang-Sup Song Fall 2010 ECE264C TuTh 11:00-12:20 Home Work #4 (Due: 11/2/10) A Miller-compensated two-stage opamp is designed for the 3b MDAC given in HW#3. Use the same capacitor values and switch sizes. Assume all NMOS bodies are connected to the negative supplies, but PMOS bodies are connected to their sources. All transistors are biased with minimum 1.5V DSsat . The minimum channel length you can use is 0.18 μ . Use the SPICE level 2 model parameters given previously. For parasitic capacitances, assume the minimum S/D width is
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Unformatted text preview: 0.5 . Set the device sizes of M 1 through M 8 and the values of C c and R z to have a closed-loop gain and bandwidth for 10b settling with a phase margin of >60 o . The supply voltage is 1.8V. You are free to simulate using SPICE, but the SPICE output alone is not accepted as a homework solution without your design. Your hand calculations should include the effect of the opamp input capacitance. For SPICE simulations, you need to apply common-mode feedback for proper biasing. M 1 C c R z M 2 M 3 M 4 M 5 M 6 M 7 M 8...
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