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hw3 - of the half clock period 4 Finish the switch...

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UNIVERSITY OF CALIFORNIA, SAN DIEGO Department of Electrical and Computer Engineering Bang-Sup Song Fall 2010 ECE264C TuTh 11:00-12:20 Home Work #3 (Due: October 21, 2010) A 3b MDAC during the amplification phase is shown below together with its residue plot. It is the first-stage residue amplifier of a 10b 100MS/s pipelined ADC. Use the same device parameters given in HW#2. The later pipelined stages are assumed to be the same as this stage, and the 6 comparators also load this stage with an additional total capacitor of 0.5pF. 1. Set the nominal capacitor size of C1~C4 to have an SNR of 65dB neglecting the opamp noise. 2. Set the top-plate switch size and the bottom-plate CMOS switch sizes. 3. Sketch a resistor-string voltage divider to supply the 6 reference voltages for the comparators, and set the resistor values so that the RC time constant is shorter than 1/20
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Unformatted text preview: of the half clock period. 4. Finish the switch connections for the capacitor bottom plates when the sampled input is differential -0.36V, and what is the amplified residue output? 5. If the opamp input capacitance of each input terminal is 0.5pF, what is the minimum opamp open-loop unity-gain bandwidth and DC gain? 6. Assume C1~C4 have the actual values slightly off from the nominal value by -0.03%, +0.05%, -0.08%, +0.06%, respectively. What are the DNL and INL at a 10b level if opamp is ideal? C1 C2 C3 C4 0.6V 0.9 1.2V 1 0 -1 1 0 -1 1 0 -1 C1 C2 C3 C4 0.6V 0.9V 1.2V 1 0 -1 1 0 -1 1 0 -1 Input Range Output Range Coarse 6 Comparator Levels-1 -1 -1 0 -1 -1 0 0 -1 1 1 b 2 ± + + ±...
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