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hw2 - switch on-resistance M 4 and M 5 are set to be the...

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UNIVERSITY OF CALIFORNIA, SAN DIEGO Department of Electrical and Computer Engineering Bang-Sup Song Fall 2010 ECE264C TuTh 11:00-12:20 Home Work #2 (Due: October 14, 2010) As discussed in the class, the following is a standard bottom-plate S/H circuit. Non- overlapping two-phase clocks, ± 1 and ± 2 are non-overlapping. Assume that the differential op amp is ideal for now, and doesn’t contribute to noise. You are to design the capacitor and transistor sizes of the sampling circuit. The supply voltage is 1.8V, and the signal common-mode ground V ic is 0.9V. The input signal swing is 1V differential. The sampling frequency is 20MHz, and the input bandwidth is 10MHz. The sampling circuit settles with 0.01% accuracy. The minimum channel length to use for all switches is 0.18 μ . Use the following SPICE parameters. 1. Set the sampling capacitor value so that you have an SNR of 70dB. 2. Set the device sizes of M 1 , M 2 , M 3 so that the bottom switch on-resistance is 1/5 of the top
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Unformatted text preview: switch on-resistance. M 4 and M 5 are set to be the same as M 2 and M 3 . 3. If W/L of two switches M 1 are mismatched by 5%, what is the sampled output offset voltage? 4. If the opamp DC gain is 70dB, what is the output swing with a 10MHz, 1V differential input? 5. First estimate the % linearity error of the bottom switch differential on-resistance by checking three inputs of 0, 0.5, and 1V. Assuming that the peak error is the magnitude of the dominant harmonic, estimate THD. .MODEL MN NMOS LEVEL=2, VTO=0.25V, LD=0.04U, UO=210, TOX=4E-09, +CGSO=230P, CGDO=230P, TPG=1, NSUB=3.7E17, MJ=0.4, CJ=1030U, +CJSW=130P, MJSW=0.3, XJ=0.1U, GAMMA=0.4, PHI=0.6, LAMBDA=0.1 .MODEL MP PMOS LEVEL=2, VTO=-0.25V, LD=0.04U, UO=80, TOX=4E-09, +CGSO=200P, CGDO=200P, TPG=-1, NSUB=6E17, MJ=0.4, CJ=1040U, +CJSW=170P, MJSW=0.3, XJ=0.1U, GAMMA=0.4, PHI=0.6, LAMBDA=0.1...
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