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Unformatted text preview: switch on-resistance. M 4 and M 5 are set to be the same as M 2 and M 3 . 3. If W/L of two switches M 1 are mismatched by 5%, what is the sampled output offset voltage? 4. If the opamp DC gain is 70dB, what is the output swing with a 10MHz, 1V differential input? 5. First estimate the % linearity error of the bottom switch differential on-resistance by checking three inputs of 0, 0.5, and 1V. Assuming that the peak error is the magnitude of the dominant harmonic, estimate THD. .MODEL MN NMOS LEVEL=2, VTO=0.25V, LD=0.04U, UO=210, TOX=4E-09, +CGSO=230P, CGDO=230P, TPG=1, NSUB=3.7E17, MJ=0.4, CJ=1030U, +CJSW=130P, MJSW=0.3, XJ=0.1U, GAMMA=0.4, PHI=0.6, LAMBDA=0.1 .MODEL MP PMOS LEVEL=2, VTO=-0.25V, LD=0.04U, UO=80, TOX=4E-09, +CGSO=200P, CGDO=200P, TPG=-1, NSUB=6E17, MJ=0.4, CJ=1040U, +CJSW=170P, MJSW=0.3, XJ=0.1U, GAMMA=0.4, PHI=0.6, LAMBDA=0.1...
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This note was uploaded on 01/08/2011 for the course CSE cse105 taught by Professor Cs during the Fall '10 term at UCSD.
- Fall '10