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sample_final - 1 Please show all work clearly — no work...

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Unformatted text preview: 1. Please show all work clearly — no work, no credit; 2. Work hard to follow will be down graded- make sure to label all signals; 3. Please read each problem carefully and follow the instructions given in the problem precisely. 1. 21) Find the truth table for the circuit shown below. b) Redesign the circuit using only two—input NAND gates and inverters. Reduce the gate count as much as possible in your new design. a E 9 K1 F” N v11 CL 2‘? F=W15+><Ws+o39e a 0 i ‘ , o . 'TX‘er C) U ‘i’ ‘ : S(w5+wg)+j(xg+§;) 1 o i 8 y D 0' 0 o i 1, i E) I 0 5 u ‘ a I 0 % 5:J>3_ . ‘9‘! 2%... . ‘ T 2. A synchronous sequential circuit accepts one serial input, x, and produces one serial output, f. f=1 whenever two or more consecutive inputs are of the same value (i.e., all 0’s or all 1’s), otherwise f=0. A second input, y, resets the circuit. That is, when y=1, then f=0. After y changes from 1 to 0, the circuit needs to see two or more consecutive 0’s or 1’s again from its x input in order to produce f=1. Design the sequential circuit using D FPS and logic gates. . C‘IH Li A:00 P):c'v (:10 Clack 3. a) A 256M x 4 RAM chip uses coincident decoding. Assuming that the RAM storage cell array is square, what are the sizes of its internal row and column decoders? How many such chips are needed to form a 1G x 8 main memory? Show calculations. . ’ 25¢ MX4 : I5! taxi; .=> 250534: =5 lib/weds >r zlgc‘aiuwv‘s. (W dict-dye: IS’ it iguixwtfzxu » '3‘ ' Column (L‘LcozlzL : 115/4 : 2‘g => (3 E 2 é’éZ atré/L . %— = 4X2 1 8 CLUFS => 4 I'LWS .5: 2. (oi/(Anna: 2 b) ‘ Show the circuit diagram of the 1G x 8 memory. of part a). Make sure to label all signals. A two~word instruction has its op-code part stored in memory location 200 and its address part in location 201. The content in memory location 201 is 400 and the content in location 400 is 800. A register, R1 contains the number 500. What would be the effective address if the addressing mode of the instruction is a) direct; b) immediate; c) memory indirect; d) relative; e) indexed with R1 as the index register. a). difiacl' EA :400 l7). i-mvwaticqfl EA : lei c) met/vim] Cvtdiud' EA : go? A) ’UL'ax‘i’in "A = 2014—4160 : 602 9) {“de 5A 1 400+§wc : (for; 4. a) Given the dataflow unit block diagram and the control word encoding below, for each register transfer operation indicated, complete the value of the control word. Make use of don’t cares when appropriate. Encoding of Control Word for the Dntapnfll DA, AA, BA MB F8 MD RW Function Code chtion Cndl Function Code Function Code Function Coda RU 000 Register 0 Fé—A 0000 Function 0 No write 0 RI 001 Constant 1 FQ—Ai-i 0001 Data [n 1 Write 1 R2 010 F <— A + B 0010 R3 011 Fe—A+l_{+l' 0011 R4 m F 9.4+ B 0100 RS 101 MAUI“ 0101 R6 110 F +- A — l 0110 R7 1 11 F e- A 0111 F e-AAB 1000 F 4—AvB 1(1)! F (—A% B 1030 F ‘_ 7" 1011 Ft—B “00 F s—sr I} 1101 F esl B 1110 In immediate mode, BA is used as the immediate data 151113123110 9‘ 1' 6 3 d 3 2 annual-an (h) (bud m —l--flgfil - Oeration —-m-— o . or ——-~-—=fl —--—-—-- _----—III -—II-- 5. A functional unit is capable of performing the operations shown below, where A and B are operands and F is the result. Show the design of a typical bit of the function unit using components from the following list: multiplexers, decoders, gates, and a parallel adder. Make sure to include the circuit for cm to the parallel adder. m Qperatiog 000 decrement (F=A-l) 001 add (F=A+B) A (“14‘ 010 subtract (F=A-B) 011 increment (F=A+l) 100 transfer (F=A) 101 AND (F=A&B) 110 OR (F=AIB) 111 complement (F=A’) Load“. ...
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