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t2 - d If the number B is stored in a switched-tail ring...

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Engr 356 Basic Computer Architecture Test #2 (11-3-2010) ______________________________ Name NOTE: Be sure to label all signals Reduce the number of circuit elements used is always an implied requirement for all design problems 1. Design a full adder using a decoder and two logic gates, if needed. Show the interconnections of 4 such adders (you may use a simple box to represent a full adder here but make sure to show all inputs and outputs) to form a 4-bit ripple adder. 2. Implement the logic function, F = B’(A + C + D) + BC’, using only 4-input MUXs and one inverter, if needed.
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3. Let A = -23 and B = +32 be two signed decimal numbers. a) Express A and B in signed binary number format (with negative numbers in the 2’s complete form) b) Perform A-B using binary addition [i.e., A + (-B)]. Is the result correct? c) Obtain the result of performing two arithmetic right shifts to the number A
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Unformatted text preview: d) If the number B is stored in a switched-tail ring counter, what is the content of this counter after 2 clocks? 4. The diagram below is a “typical stage i” of a register (with its neighboring stage i+1 shown in the dashed box). Analyze the circuit by going through sequential circuit analysis procedures including combinational analysis, state transition and state table, and state diagram. What operations can this register perform? I i 1 0 MUX s X clock D D i+1 i Q Q 5. Design a variable length counter using SR FFs and NAND gates. The control input, C, controls the length of the count: If C=1, the counting sequence is 0,1,0,1,…. If C=0, the sequence is 0,1,2,0,1,2,…. The next state of any unused state should be 0. Show all design steps starting with a state diagram....
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