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Unformatted text preview: d) If the number B is stored in a switchedtail ring counter, what is the content of this counter after 2 clocks? 4. The diagram below is a “typical stage i” of a register (with its neighboring stage i+1 shown in the dashed box). Analyze the circuit by going through sequential circuit analysis procedures including combinational analysis, state transition and state table, and state diagram. What operations can this register perform? I i 1 0 MUX s X clock D D i+1 i Q Q 5. Design a variable length counter using SR FFs and NAND gates. The control input, C, controls the length of the count: If C=1, the counting sequence is 0,1,0,1,…. If C=0, the sequence is 0,1,2,0,1,2,…. The next state of any unused state should be 0. Show all design steps starting with a state diagram....
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 Fall '08
 Valverde
 Computer Architecture, Binary numeral system, Decimal, Binarycoded decimal

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