Assignment 2

Assignment 2 - EE 2000 Logic Circuit Design Semester A...

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EE 2000 Logic Circuit Design, Semester A, 2007/08 Assignment 2 (Total Marks: 70) Deadline: 9 th November, 2007 (Week 10 Friday) Submission instruction: Write your answer on paper and show your steps clearly. Indicate you Name, Student ID and Course Session (C01 or C61) on the answer sheets. Please submit to the instructor at the beginning of the lecture. Question 1: The following figure shows the block diagram of a circuit which has four inputs A , B , C , D and one output Y . It operates according to the following rules: (i) If the inputs A , B , C and D have more 0s than 1s, the circuit will generate an odd parity bit for the inputs. (ii) If the number of 0s and 1s of the inputs are equal, the machine will generate an even parity for the inputs. (iii) If there is only one 0, the output is equal to 1. (iv) The output of the remaining case(s) is (are) 1. Block diagram of a 4 inputs to 1 output circuit (a) Tabulate the truth table of the circuit. (b) By considering the minimum SOP expression of the truth table, design the

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This note was uploaded on 01/11/2011 for the course EE 2000 taught by Professor Vancwting during the Fall '07 term at City University of Hong Kong.

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Assignment 2 - EE 2000 Logic Circuit Design Semester A...

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