04 Combinational Logic Design

# 04 Combinational Logic Design - EE2000 Logic Circuit Design...

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1 EE2000 Logic Circuit Design Combinational Logic Design

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2 Outline ± Design Procedure ± Code Converter ± Combinational Functional Blocks ± Arithmetic Functional Blocks ± Adder, Subtractor, Comparator ± Timing Hazard
3 Design Procedure ± Specification : write a specification for the circuit ± Formulation : derive the truth table (or initial Boolean equations) to define the relationships between inputs and outputs ± Optimization : apply logic circuit optimization ± Technology Mapping : transform logic diagram to a new diagram using available implementation technology ± Verification : verify the correctness of the final design

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4 Design Example 1 ± Design of a BCD-to-Excess-3 Code Converter ± Specification: ± XS3 code for a decimal digit is the binary combination corresponding to the decimal digit plus 3 ± Each BCD digit labeled from MSB, A , B , C , D ± The XS3 digit labeled from MSB, W , X , Y , Z ± i.e. ( ABCD ) BCD = ( WXYZ ) XS3
5 What We Want to Do Is ± Design a logic circuit that perform conversion ± Input is BCD code ± Output is Excess-3 code A B C W X Y Z D Excess-3 code BCD code ?

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6 XS3 Code Converter ± Formulation: ± The truth table relating input and output variables Output Excess-3 Input BCD 0 1 0 1 1 1 1 0 7 1 1 0 1 0 0 0 1 8 0 1 0 1 0 1 0 1 Z 0 0 0 1 1 0 0 1 Y 0 1 1 1 0 0 0 0 B 1 0 0 0 0 0 0 0 A 1 0 1 0 1 0 1 0 D 0 1 0 0 1 1 0 0 C 1 0 0 1 1 1 1 0 X 1 1 1 0 0 0 0 0 W 4 5 6 3 9 2 1 0 Decimal digit Some input combinations are not listed here as no meaning in BCD code. We can treat them as don’t care conditions
7 XS3 Code Converter ± Optimization: ± There are four variables ( A , B , C , D ) in the functions ± Each output variable depends on 4 variables ± So we need 4 four-variable K-maps ± W ( A , B , C , D ) = Σ m (5, 6, 7, 8, 9) + Σ d (10, 11, 12, 13, 14, 15) ± X ( A , B , C , D ) = Σ m (1, 2, 3, 4, 9) + Σ d (10, 11, 12, 13, 14, 15) ± Y ( A , B , C , D ) = Σ m (0, 3, 4, 7, 8) + Σ d (10, 11, 12, 13, 14, 15) ± Z ( A , B , C , D ) = Σ m (0, 2, 4, 6, 8) + Σ d (10, 11, 12, 13, 14, 15)

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8 1 0 0 0 1 x 1 x 1 0 0 0 1 1 1 1 0 A B C D 1 1 1 1 1 0 x x x x 1 1 0 0 0 1 x x 1 0 0 0 1 1 1 1 0 A B C D 1 1 1 1 1 0 x x x x 1 1 0 0 0 1 x 1 x 0 0 0 1 1 1 1 0 A B C D 1 1 1 1 1 0 x x x x 1 1 0 0 0 1 x 1 x 0 0 0 1 1 1 1 0 A B C D 1 1 1 1 1 0 x x x x K-map for W : K-map for X : K-map for Y : K-map for Z :
9 1 0 0 0 1 x 1 x 1 0 0 0 1 1 1 1 0 A B C D 1 1 1 1 1 0 x x x x 1 1 0 0 0 1 x x 1 0 0 0 1 1 1 1 0 A B C D 1 1 1 1 1 0 x x x x 1 1 0 0 0 1 x 1 x 0 0 0 1 1 1 1 0 A B C D 1 1 1 1 1 0 x x x x 1 1 0 0 0 1 x 1 x 0 0 0 1 1 1 1 0 A B C D 1 1 1 1 1 0 x x x x W = A + BC + BD X = B’C + B’D + BC’D’ Y = CD + C’D’ Z = D’

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10 Factoring the Common Terms ± From the pervious K-maps, ± W = A + BC + BD ± X = B’C + B’D + BC’D’ ± Y = CD + C’D’ ± Z = D’ ± We further optimize them ± W = A + BC + BD = A + B ( C + D ) ± X = B’C + B’D + BC’D’ = B’ ( C + D ) + B ( C+D )’ ± Y = CD + C’D’ = CD + ( C+D )’ DeMorgan’s theorem
11 The Final Logic Diagram A B C W X Y Z D

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12 Design Example 2 ± Design of a BCD-to-Seven-Segment Converter ± Specification: ± The decoder accepts a decimal digit in BCD and generates the appropriate outputs for the 7 segments of the display for that decimal digit ± Each BCD digit labeled from MSB, A , B , C , D ± The seven outputs controlling the segments labeled as, a , b , c , d , e , f , g
13 Seven Segment Displays a b c d e f g 0123456789 Light on (1) Light off (0) A B C a b c d D a,b,c,d,e,f = 1 g = 0 ?

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## This note was uploaded on 01/11/2011 for the course EE 2000 taught by Professor Vancwting during the Fall '07 term at City University of Hong Kong.

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04 Combinational Logic Design - EE2000 Logic Circuit Design...

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