05 Larger Combinational Systems (Part A)

05 Larger Combinational Systems (Part A) - EE2000 Logic...

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1 EE2000 Logic Circuit Design Larger Combinational Systems
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2 Outline ± Decoder, with and without Enabling ± Encoder, with Priority ± Multiplexers ± Demultiplexers ± Programmable Logic Devices ± ROM ± PLA ± PAL
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3 Decoder ± How many number can a n -bit binary represent? ± A decoder is a combinational circuit with n - input and m -output (0 < n m 2 n , but usually m = 2 n ) ± A very important functional blocks as it can be incorporated into many of the other functions
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4 ± Design a logic circuit that decodes a binary number ± Input: binary number ( A : A 2 A 1 A 0 ) ± Output: D k = 1 where k is the decimal value of A , all other D i = 0 (for all i = 0 to 2 n , i k ) What We Want to Do Is A 2 A 1 A 0 Binary no. D 1 D 0 D 3 D 2 D 4 D 5 D 7 D 6 BIN / DEC
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5 Decoder: Formulation ± The truth table ± 3-input, 8-output 0 0 0 0 1 0 0 0 D 3 0 0 0 0 0 1 0 0 D 2 0 0 0 0 0 0 1 0 D 1 0 0 0 0 0 0 0 1 D 0 1 0 1 0 1 0 1 0 A 0 1 1 0 0 1 1 0 0 A 1 1 1 1 1 0 0 0 0 A 2 Input (A) Output (D) 1 0 0 0 0 0 0 0 0 0 0 D 7 1 0 0 0 0 0 0 D 6 0 1 0 0 0 0 0 D 5 0 0 1 0 0 0 0 D 4 Looks like the minterm functions? 0 0 0 1 BIN / DEC 0 0 0 0 0 0 0 Example: Input (0, 0, 0) 1 1 0 0 BIN / DEC 0 0 0 0 0 0 1 Example: Input (1, 1, 0)
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6 Decoder: The Logic Diagram A 1 D D D D D D D D 0 1 2 4 5 6 7 A 2 A 0 3 = A 2 A 1 A 0 = A 2 A 1 A 0 = A 2 A 1 A 0 = A 2 A 1 A 0 = A 2 A 1 A 0 = A 2 A 1 A 0 = A 2 A 1 A 0 = A 2 A 1 A 0 Can you observe the pattern?
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7 1-to-2-Line Decoder ± Let’s see some more decoders ± Input: 1-bit ( A ) ± Output: 2-bit ( D 0 , D 1 ) 1 0 D 1 0 1 D 0 Output 1 0 A Input D 0 = A D 1 = A A BIN / DEC
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8 ± Input: 2-bit ( A 1 , A 0 ) ± Output: 4-bit ( D 0 , D 1 , D 2 , D 3 ) 2-to-4-Line Decoder 0 0 1 0 1 0 0 1 0 0 0 1 0 0 D 1 0 1 D 0 1 0 A 1 1 0 D 1 0 0 D 0 Output 1 0 A 0 Input D 0 = A 1 A 0 A 0 A 1 D 1 = A 1 A 0 D 2 = A 1 A 0 D 3 = A 1 A 0 BIN / DEC 2 1-to-2-line decoders 4 2-input ANDs Construct a 2-to-4-line decoder using 1-to-2-line decoders and AND gates
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9 How about 3-to-8-Line Decoder? D 2-4-0 A 0 A 1 2-to-4-line decoders 8 2-input ANDs A 2 1-to-2-line decoders D 2-4-1 D 2-4-2 D 2-4-3 D 0 = A 2 D 2-4-0 D 1 = A 2 D 2-4-1 D 2 = A 2 D 2-4-2 D 3 = A 2 D 2-4-3 D 4 = A 2 D 2-4-0 D 5 = A 2 D 2-4-1 D 6 = A 2 D 2-4-2 D 7 = A 2 D 2-4-3 Can be constructed using 2-to-4-Line and 1-to-2-Line decoders 2 0 2 1 2 2
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10 Decoder with Enabling ± A 2-to-4-line decoder with enable input ± For EN to 0 (i.e. disabled), all outputs of the decoder are 0 ± For EN to 1 (i.e. enabled), one outputs is 1 (determined by A 1 , A 0 ), and all others are 0 0 0 0 0 x x 0 1 1 1 1 EN 0 0 1 0 1 0 0 1 0 0 0 1 0 0 D 1 0 1 D 0 1 0 A 1 1 0 D 1 0 0 D 0 Output 1 0 A 0 Input
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11 2-to-4-line Decoder with Enabling D 2-4-0 A 0 A 1 2-to-4-line decoders D 2-4-1 D 2-4-2 D 2-4-3 2 0 2 1 EN D 0 D 1 D 2 D 3 Enabling circuits EN A 1 A 0 D 1 D 0 D 3 D 2 Decoder The corresponding symbol of 2-to-4-line decoder with enabling
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This note was uploaded on 01/11/2011 for the course EE 2000 taught by Professor Vancwting during the Fall '07 term at City University of Hong Kong.

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05 Larger Combinational Systems (Part A) - EE2000 Logic...

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