06 Flip-flops - EE2000 Logic Circuit Design Sequential Circuits Flip-Flops 1 Outline Latches Gated Latches SR,SR and D Latches Flip-Flops

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1 EE2000 Logic Circuit Design Sequential Circuits Flip-Flops
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2 Outline ± Latches ± Gated Latches ± SR , S’R’ , and D Latches ± Flip-Flops ± Master-Slave Flip-Flops ± Edge-Triggered Flip-Flops ± SR , D , JK and T Flip-flops ± Synchronous and Asynchronous Inputs ± Timing parameters
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3 Introduction ± Two classes of logic circuits ± Combinational logic circuits ± Sequential circuits ± Up to now, studied only combinational logic circuits ± Outputs depend only on what the inputs are present at the moment ± Sequential circuits ± Outputs depend not only on present inputs, but also on past history (sequence) of inputs ± Therefore, past history of inputs must be preserved ± Sequential circuits are said to have memory
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4 Why Sequential Circuit? ± Sometimes system output depend on both the present and previous inputs (sequential logic) ± For example, a system with one input x and one output z such that z = 1 iff x has been 1 for at least three consecutive clock times ± Input sequence: 010011001010001110101100… ± The system must store the last three inputs of x in its memory in order to produce output based on that ± What is stored in memory is the state of the system ± Require a state table !
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5 Sequential Circuits ± Sequential circuit: interconnecting a combinational circuit and storage elements ± The binary information stored in storage elements defines the state of the sequential circuit at that time ± A sequential circuit is specified by a time sequence of inputs , internal states and outputs Combinational circuit Inputs Outputs Storage elements Present state Next state
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6 Memory ± Storage element to store information ( state ) between operations ± Basic logic elements provide memory ± Latches and flip-flops ± Two types of seq. circuits (revisit later) ± Synchronous sequential circuits ± Asynchronous sequential circuits ± This lecture note is focused on the structure and operation of several types of latches and flip-flops
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7 Basic Bistable Element ± Buffer Symbol ± How to store a value? Using feedback ± Connect the output of the buffer to its input ± Information stored for indefinite time (as long as power is applied) gate delay = t G t G t G 00 11 x (x’)’ = x Can be implemented simply using 2 inverters
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8 Basic Bistable Element xx x x x x x Q’ Q Assume x = 0, Q will be 1 and Q’ will be 0 As Q’ will feedback to x , new x = 0 again Assume x = 1, Q will be 0 and Q’ will be 1 As Q’ will feedback to x , new x = 1 again Q’ Q
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9 Basic Bistable Element ± This cross-coupled circuit have two stable states ± Remains either 0 or 1 states ( bistable ) ± One more equilibrium condition – metastable state ± Two output signals about halfway between logic-0 and 1 ± Small internal change (circuit noises) could cause the output entering one of its two stable states ± Should avoid as the time is unpredictable ± This element can only store information (no inputs) ± Becomes stable in one of its two states when power is applied ± Provision must be made to force the device into a particular state ± Use NOR or NAND gates to replace the inverters
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This note was uploaded on 01/11/2011 for the course EE 2000 taught by Professor Vancwting during the Fall '07 term at City University of Hong Kong.

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06 Flip-flops - EE2000 Logic Circuit Design Sequential Circuits Flip-Flops 1 Outline Latches Gated Latches SR,SR and D Latches Flip-Flops

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