08 Simplification of Sequential Circuits

# 08 Simplification of Sequential Circuits - EE2000 Logic...

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1 EE2000 Logic Circuit Design Simplification of Sequential Circuits

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2 Mealy Machine Model Inputs X i Outputs Z i Output Logic A Next-State Logic C B B current state excitation State Memories B : usually edge- triggered flip-flips Note: the clock inputs are omitted here
3 Moore Machine Model Inputs X i Outputs Z i Output Logic A Next-State Logic C B B current state excitation State Memories

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4 State Diagram S C S C 1/0 S A S A S B S B 0/0 1/1 0/1 1/0 0/0 S Y /0 S Y /0 0 S W /0 S W /0 S X /1 S X /1 1 1 1 0 0 Mealy Model Moore Model Node: State Line: Inputs / Outputs Node: State / Outputs Line: Inputs
5 What You Have Learnt ± Two State Machine Models ± Mealy Model ± Moore Model ± State Diagram and State Table ± Two Typical Examples ± Sequence Recognizer ± Modulo- n Counter

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6 Combination Logic Circuit ± In designing combination logic circuits, ± Read the specification ± Derive the truth table ± Minimize the output functions by ± Boolean algebra, K-map, or Q-M method ± In designing sequential logic circuits, ± Read the specification ± Derive the state diagram and state table ± Minimize the state table (how?)
7 Outline ± Redundant State Elimination ± Inspection ± Partitioning ± Implication Table ± Sequential Circuit Analysis ± Design with Programmable Logic Device

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8 State Table ± An example of state table has been shown on the right hand side ± How many flip-flops required to implement this sequential circuit? ± Since 15 states, ± Need 4 flip-flops (why?) S A / 1 S A / 0 S J S B / 0 S A / 0 S K S A / 1 S A / 0 S L S B / 0 S A / 0 S M S B / 0 S A / 0 S N S M / 0 S L / 0 S F S P / 0 S N / 0 S G S B / 0 S A / 0 S H S B / 0 S A / 0 S I S G / 0 S F / 0 S C S I / 0 S H / 0 S D S K / 0 S J / 0 S E Input X Present State (PS) S A / 0 S D / 0 S B / 0 0 S B / 0 S P S E / 0 S C / 0 1 S B S A
9 Redundant State Elimination ± For combination logic circuits, minimizing the output functions means ± Reducing the number of logic gates ± i.e. reducing the cost and also space of the circuit ± For sequential logic circuits, minimizing the state table means ± Reducing the redundant states ± i.e. reducing the number of flip-flops ± Reducing the cost and space ± Also, if too many flip-flops, require Q-M to simplify the output functions and flip-flip input functions (why?)

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10 Concept of Equivalent States ± Are these two state diagram equivalent? S C S C 1/0 S A S A S B S B 1/1 1/1 0/1 0/0 0/0 S D S D 0/1 1/1 1/0 S A S A S B S B 1/1 0/1 0/0 S D S D 0/1 1/1 S C S C
11 Concept of Equivalent States ± Compare their state table S A / 1 S D / 0 S C S A / 1 S D / 1 S D Input X Present State (PS) S D / 0 S B / 1 0 S A / 1 S C / 0 1 S B S A S A / 1 S D / 1 S D Input X Present State (PS) S D / 0 S D / 0 S B / 1 0 S A / 1 S A / 1 S C / 0 1 S B S C S A S C S C 1/0 S A S A S B S B 1/ 1 1/1 0/1 0/0 0/0 S D S D 0/1 1/1 1/0 S A S A S B S B 1/1 0/1 0/0 S D S D 0/1 1/1 S C S C S B

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12 Concept of Equivalent States ± If there are two states that given the same input conditions
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## This note was uploaded on 01/11/2011 for the course EE 2000 taught by Professor Vancwting during the Fall '07 term at City University of Hong Kong.

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08 Simplification of Sequential Circuits - EE2000 Logic...

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