09 Sequencial Functional Blocks

# 09 Sequencial Functional Blocks - EE2000 Logic Circuit...

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1 EE2000 Logic Circuit Design Sequential Functional Blocks Registers and Counters

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2 Introduction ± We studied the concept of functional blocks in combinational logic circuit ± Combinational functional blocks ± e.g. adder, subtractor, comparator, decoder, encoder, multiplexer, demultiplexer, etc ± How about functional blocks in sequential logic circuits? ± Sequential functional blocks ± e.g. register and counter
3 Why Functional Blocks? ± Designing logic circuit is tedious ± Combinational logic circuit: ± Write the truth table Simplify output functions Draw the circuit diagram ± Sequential logic circuit: ± Draw the state diagram Minimize the state table Simplify the flip-flop input equations and output functions Draw the circuit diagram ± Build circuits that is structural for easier expansion ± e.g. one-bit full adder n -bit full adder ± 1-to-2-line MUX n -to-2 n -line MUX ± How about registers and counters ?

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4 Outline ± Registers ± Parallel Load ± Shift Registers ± Applications ± Serial Data to Parallel Data (and vice versa) ± Serial Adder, Accumulator ± Counters ± Synchronous, and Asynchronous Counters ± Ripple Counter, Up-Down Counter, Modulo Counter, Ring Counter
5 Registers ± Memory used for storing (binary) information during the processing of data ± To store n -bit data, require n flip-flips ± n -bit register ± Composed of a set of n edge-triggered flip-flops ± The clock pulse is the enable signal ± Data will be latched to the flip-flops during the clock active period (pos. edge or neg. edge) ± Two designs ± Parallel, or Serial

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6 4-bit Register C D Q Q PRE CLR C D Q Q PRE CLR C D Q Q PRE CLR C D Q Q PRE CLR Clk Parallel data input ( PI ) D 0 D 1 D 2 D 3 Parallel data output ( PO ) Q 0 Q 1 Q 2 Q 3 Note: PRE’ & CLR’ inputs are not drawn in this diagram
7 4-bit Register ± As see from last page, constructed from 4 D - type positive-edge-triggered flip-flops ± The register loads all four D inputs into the flip- flops in parallel (at the positive clock transition) ± Advantage of this design ± Simple, just group the flip-flops together ± Not require any external logic gates ± Disadvantage? ± No enabling! C D 0 Q 0 PRE CLR D 1 D 2 D 3 Q 1 Q 2 Q 3 REG Logic Symbol

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8 Flip-Flops with Enable ± At the moment of positive clock transition (negative clock transition for NET-FF), ± If Load = 1 (i.e. EN = 1), the register will load the 4 data inputs into the flip-flops ± If Load = 0 (i.e. EN = 0), the register will hold its memory remain unchanged ± Have not learnt this kind of flip-flops? ± We can design FF with enable on our own ± How?
9 ± The truth table ± Therefore, the flip-flip input equation is ± D A = Load’ · Q + Load · D PET D Flip-Flops with Enable Parallel Load Hold Disable Operation D Q Q Next Q Outputs 0 x ,0,1 Clk 1 X Load x x D Inputs C D Q Q PRE CLR Load (EN) D Clk Flip-flop with enable C D Q Q PRE CLR EN D A Logic Symbol

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09 Sequencial Functional Blocks - EE2000 Logic Circuit...

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