10 Logic Families - EE2000 Logic Circuit Design Logic...

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1 EE2000 Logic Circuit Design Logic Families Characteristics of Logic Gates
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2 Outline ± Electrical Characteristics of Logic Gates ± Logic Levels ± Noise Margins ± Speed of Operation ± Power Dissipation ± Operation Temperature ± Fan-in, Fan-out ± Comparison of Families ± TTL,CMOS, and ECL ± Interfacing between different families
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3 An Ideal Inverter V in Time GND V CC V out Time GND V CC Input to the inverter Output of the inverter
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4 Electrical Characteristics ± Ideal Electrical Characteristics ± The input circuit has no loading effect on the driving signal (i.e. the output of previous gate) since R in = and the sink current is zero ± The output is capable of driving any arbitrary number of similar gates without signal degrading (this is a direct consequence of zero sink current) ± Most practical gates are non-ideal
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5 Electrical Characteristics ± For practical gates, the following features have to be considered during selection of appropriate gate type to ensure a specified performance ± Range of voltages correspond to the logic 0 and 1 levels ± Uncertainty region for these logic levels, i.e. noise margin ± Switching speed ± Static and dynamic power dissipation ± Input and output loading effects ± Operating temperature ± Supply voltage limits
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6 Logic Levels ± Ideal logic levels ± Logic 0: Ground ± Logic 1: V CC ± For practical gates, the outputs voltage have to be defined ± V OH : the minimum value of output logic 1 ± V OL : the maximum value of output logic 0 ± Uncertainty region: region between V OH and V OL
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7 Logic Levels ± Similarly for the inputs , ± V IH : the minimum value for input logic 1 ± V IL : the maximum value for input logic 0 ± Uncertainty region: region between V IH and V IL ± Note: input level within this region to a logic gate will not provide a clear output level ± i.e. can either be HIGH (logic 1) or LOW (logic 0)
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8 Output Logic Levels: V OH , V OL V out Time V OL V OH Minimum value for logic 1 output Maximum value for logic 0 output Valid region for logic 0 output Valid region for logic 1 output Uncertainty region Output = logic 1 Output = logic 0 Output = ?? Output = ?? GND V CC
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9 Input Logic Levels: V IH , V IL V in Time V OL V OH Minimum value for logic 1 input Maximum value for logic 0 input Valid region for logic 0 input Valid region for logic 1 input Uncertainty region Input = logic 1 Input = logic 0 Input = ?? Input = ?? V IL V IH The range of valid input voltage are normally larger than that of the valid output range GND V CC
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10 Noise Margin ± Noise is unwanted signal present in the electric circuit ± Ideally, noise should not alter the logic states ± If the noise level exceeds the margin in the uncertainty region , it can trigger the transition ± The margin is known as noise margin ± NM H = V OH V IH (Noise Margin for logic 1) ± NM L = V IL - V OL (Noise Margin for logic 0)
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11 Noise Margin: NM H , NM L NM H NM L uncertainty region v o v i V OH V OL V IL V IH output of gate 1 input of gate 2
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This note was uploaded on 01/11/2011 for the course EE 2000 taught by Professor Vancwting during the Fall '07 term at City University of Hong Kong.

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10 Logic Families - EE2000 Logic Circuit Design Logic...

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