Tutorial 9 Solution - Q . CLR’ J K PRE’ Clk Q Question...

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EE 2000 Logic Circuit Design, Semester A, 2007/08 Tutorial 9 Solution Level 1 Hints: Always draw the dot lines that aligned to the edges of input signals first Question 1: Two edge-triggered SR flip-flops are shown in the following figure. If the inputs are as shown, sketch the Q i outputs of each flip-flop relative to the clock, and explain the difference between the two. The flip-flops are initially RESET. Q 1 responses to the inputs at the rising edges only while Q 2 responses to the input at the falling edges only. Q 2 S R Q 1 Q 1 Clk S R Q Q C S R Q Q C Q 2
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Question 2: Determine the Q waveform relative to the clock if the signals shown in the following figure are applied to the inputs of the JK flip-flop. Assume that Q is initially LOW. CLR’ J K PRE’ PRE’ Clk J K Q Q C CLR’ Q
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Question 3: The waveforms of the following figure are applied to the inputs of an SN7476 JK flip flop (negative-edge triggered). Complete the timing diagram by sketching the waveforms of flip-flop output
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Unformatted text preview: Q . CLR’ J K PRE’ Clk Q Question 4: The circuit of the following figure contains a D latch, a positive-edge-triggered D flip-flop, and a negative edge-triggered D flip-flop. Complete the following timing diagram by sketching the waveform of signals Q 1 , Q 2 and Q 3 . Q 3 Clk Q 1 Q 2 x D Q Q C D Q Q C Clk x Q 1 Q 2 Q 3 D Q Q C Level 2 Question 5: A SR flip-flop is connected as shown in the following figure. Determine the Q output in relation to the clock. What specific function does this device perform? Q will toggle its value at the rising edge of the clock. Q S R Q Q C Clk Question 6: The circuit of the following figure contains a negative edge–triggered T flip-flop and D flip-flop. Complete the following timing diagram by sketching the waveforms of signals Q 1 and Q 2 . Q 2 lags Q 1 by one period of clock signal. Q 2 Clk CLR’ Q 1 x Clk x Q 1 Q 2 1 CLR’ T Q Q C D Q Q C CLR CLR...
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Tutorial 9 Solution - Q . CLR’ J K PRE’ Clk Q Question...

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