This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: SN7476 JK flip flop (negative-edge triggered). Complete the timing diagram by sketching the waveforms of flip-flop output Q . Question 4: The circuit of the following figure contains a D latch, a positive-edge-triggered D flip-flop, and a negative edge-triggered D flip-flop. Complete the following timing diagram by sketching the waveform of signals Q 1 , Q 2 and Q 3 . Q 3 Clk Q 1 Q 2 x D Q Q C D Q Q C Clk x Q 1 Q 2 Q 3 D Q Q C CLR’ J K PRE’ Clk Q Level 2 Question 5: A SR flip-flop is connected as shown in the following figure. Determine the Q output in relation to the clock. What specific function does this device perform? Question 6: The circuit of the following figure contains a negative edge–triggered T flip-flop and D flip-flop. Complete the following timing diagram by sketching the waveforms of signals Q 1 and Q 2 . Q 2 Clk CLR’ Q 1 x Clk x Q 1 Q 2 1 CLR’ T Q Q C D Q Q C CLR CLR Q S R Q Q C Clk...
View Full Document
- Fall '07
- Logic gate, Latch, following figure