Tutorial 10 Solution - EE 2000 Logic Circuit Design...

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EE 2000 Logic Circuit Design, Semester A, 2007/08 Tutorial 10 Solution Level 1 Question 1: In the lecture you were told that sequential system with Mealy model usually requires fewer states than Moore model. Now you are going to verify this by revisiting the same example in last lecture. Design a Moore system sequence recognizer with one input x and one output z such that z = 1 iff x has been 1 for three consecutive clock times. Input sequence x : 01101110011111100 Output sequence z : ?0000001000011110 (Moore model) Output sequence z : 00000010000111100 (Mealy model) (a) Draw the state diagram (b) How many states are there? Please compare with that of the Mealy model Ans: (a) (b) Moore model requires 4 states while Mealy model requires 3 states only. Nothing recognized “1” “11” “111” S A / 0 S B / 0 S C / 0 S D / 1 0 111 0 0 0 1
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Question 2: The example of the “111” sequence recognizer in last lecture assumed that overlapping of inputs is allowed. What if overlapping of inputs is not allowed? An
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This note was uploaded on 01/11/2011 for the course EE 2000 taught by Professor Vancwting during the Fall '07 term at City University of Hong Kong.

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Tutorial 10 Solution - EE 2000 Logic Circuit Design...

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