Tutorial 10 - 01101110011111100 Output sequence z :...

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EE 2000 Logic Circuit Design, Semester A, 2007/08 Tutorial 10 Level 1 Question 1: In the lecture you were told that sequential system with Mealy model usually requires fewer states than Moore model. Now you are going to verify this by revisiting the same example in last lecture. Design a Moore system sequence recognizer with one input x and one output z such that z = 1 iff x has been 1 for three consecutive clock times. Input sequence x : 01101110011111100 Output sequence z : ?0000001000011110 (Moore model) Output sequence z : 00000010000111100 (Mealy model) (a) Draw the state diagram (b) How many states are there? Please compare with that of the Mealy model Question 2: The example of the “111” sequence recognizer in last lecture assumed that overlapping of inputs is allowed. What if overlapping of inputs is not allowed? An example of input/output sequences that satisfy the circuit specifications is as follow: Input sequence x :
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Unformatted text preview: 01101110011111100 Output sequence z : 00000010000111 100 (If overlapping is allowed) Output sequence z : 00000010000100 100 (If overlapping is not allowed) Design the circuit using Mealy machine. ( To save your time, only draw the state diagram ) Question 3: Draw the state diagram of a “10101” Mealy machine sequence recognizer (a) If overlapping of inputs is allowed (b) If overlapping of inputs is not allowed Level 2 Question 4: Using JK FFs and with the minimum number of states to design a counter with counting sequence: 0,4,2,1,6 and repeat. State whether the circuit is a self-started circuit. Question 5: Design a synchronous counter using JK flip-flops with the following counting sequence and repeat. The counter will count even number when x = 0 and odd number when x = 1. When the input x is change from 0 to 1 or 1 to 0, the counter will count to the nearest higher count. x = 0 x = 1 0 1 2 3 4 5 6 7...
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Tutorial 10 - 01101110011111100 Output sequence z :...

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