Tutorial 11 Solution - EE 2000 Logic Circuit Design Semester A 2007/08 Tutorial 11 Solution Level 1 Question 1 Parallel Data Storage CLR Clk D0 C

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EE 2000 Logic Circuit Design, Semester A, 2007/08 Tutorial 11 Solution Level 1 Question 1: Parallel Data Storage. Clk CLR’ Clk CLR’ Q 0 D 3 D 0 1 D 1 D 2 Q 2 Q 1 Q 3 Register cleared Data stored Data stored D 0 D 1 D 2 D 3 Q 0 Q 1 Q 2 Q 3 D C Q Q’ CLR PRE D C Q Q’ CLR PRE D C Q Q’ CLR PRE D C Q Q’ CLR PRE Parallel Data Input Parallel Data Output
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Question 2: Frequency Division Clk CLR’ Clk CLR’ Q A 1 Q C Q B Q D Q A Q B Q C Q D T C Q Q’ CLR PRE T C Q Q’ CLR PRE T C Q Q’ CLR PRE T C Q Q’ CLR PRE Observe the period of the output waveforms. The period of Q A is twice as that of the clock signal. The period of Q B is 4 times of that of the clock signal. The period of Q B C is 8 times of that of the clock signal. The period of Q D is 16 times of that of the clock signal. Since frequency = 1 / time period Q A divides the clock frequency by 2 Q B B Time period of the clock divides the clock frequency by 4 Q C divides the clock frequency by 8 Q D divides the clock frequency by 16 Question 3: Binary Counter Clk CLR’ Q A Q C Q B Q D 1 1 1 1 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1
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(a) This is a downward counter. As seen from the timing diagram in last question. The
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This note was uploaded on 01/11/2011 for the course EE 2000 taught by Professor Vancwting during the Fall '07 term at City University of Hong Kong.

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Tutorial 11 Solution - EE 2000 Logic Circuit Design Semester A 2007/08 Tutorial 11 Solution Level 1 Question 1 Parallel Data Storage CLR Clk D0 C

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