EE141_HW2

EE141_HW2 - UNIVERSITY OF CALIFORNIA, BERKELEY College of...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #2 EECS141 Due Thursday, September 10, 5pm, box in 240 Cory PROBLEM 1: VTC In this problem we will analyze the noise margins for a chain of gates, Fig. 1a. The VTC has four segments, where the two curved regions can be approximated as quarter ellipses. a) Add the DC voltage sources to Figure 1.a. that you would use for modeling noise coupling to the input and output of gate M 2 . You should arrange these voltage sources so that they would both impact the noise margin in the same way (i.e., if the voltage source at the input decreases the noise margin, the voltage source at the output should also decrease the noise margin). b) Determine the noise margins (as defined in lecture) for gate M 2 when noise couples only to its input. We want a numerical answer in Volts, not one based on just looking at the VTC. c) Are the gates M4 and M5, whose VTCs are shown at the top of the next page in Figures 1.c and 1.d, digital? Is the cascade of the two gates (Figure 1.e) digital?
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 5

EE141_HW2 - UNIVERSITY OF CALIFORNIA, BERKELEY College of...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online