{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}


Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #3 EECS141 PROBLEM 1: CMOS Logic a) Implement the logic function shown below with a static CMOS gate. You can assume that both the true and complementary versions of input are available (e.g. and are available simultaneously). b) Someone claims they can build a static AND gate with the circuit shown below. What is wrong with this particular implementation? Vdd B A Out c) By adding just two more transistors to the circuit shown above, fix the circuit so that it will implement a static AND gate. Note that you are free to use both the true and complement versions of the input signals (A and B) to achieve this.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
PROBLEM 2: Simulation Exercise I In the following NAND2 gate, we will use the same sizing for all PMOS transistors in PUN. Similarly, all the NMOS transistors in the PDN are identically sized. We will also define the NAND2’s “ β
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}