EE141_HW3_sol

# EE141_HW3_sol - UNIVERSITY OF CALIFORNIA BERKELEY College...

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UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #3 Solutions EECS141 PROBLEM 1: CMOS Logic a) Implement the logic function shown below with a static CMOS gate. You can assume that both the true and complementary versions of input are available (e.g. and are available simultaneously). Solution: Expand the logic function in our familiar AND/OR form: Implementing this function in static CMOS: C A B B A A B B A C C A A A A B B B B Out Vdd Vdd Vdd Note that there are many other ways for this gate to be implemented (in particular many implementations that share one of the transistors for two logical terms) – any correct implementation will receive full credit. As an example, a self-dual implementation with maximum transistor sharing is shown below:

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b) Someone claims they can build a static AND gate with the circuit shown below. What is wrong with this particular implementation? Solution: There are two problems with this gate. The first and most significant one is that Out is only connected to one of the power supplies when A =1. In other words, if A =0, the output will not be driven to one of the power supplies, which does not meet the definition of a static gate. This can be shown using the truth table (“Z” stands for the output being undriven – i.e., high impedance): A B Out 0 0 Z 0 1 Z 1 0 0 1 1 “Weak 1”
As also indicated in the table, the second problem is that when A=1 and B=1, we will be passing a “1” through an NMOS transistor. In other words, the output won’t really make it all the way up to Vdd, but rather will get stuck at Vdd-V TH . c) By adding just two more transistors to the circuit shown above, fix the circuit so that it will implement a static AND gate. Note that you are free to use both the true and complement versions of the input signals (A and B) to achieve this. Solution: In order to fix the first problem, we need to connect Out to a well-defined state when A =0. Since we are building an AND gate, we know that when A =0 Out is always “0”, so we can simply add an NMOS at the output with as the gate voltage. To fix the second problem, we need to make sure we have a PMOS pulling the output up when A=B=1. Like we had discussed in lecture, we can build a switch that passes both 1’s and 0’s by placing a PMOS in parallel with an NMOS and driving it with the complementary signal at the gate, which in this case is also . With these two fixes, the circuit shown below does indeed implement a static AND gate. PROBLEM 2: Simulation Exercise I In the following NAND2 gate, we will use the same sizing for all PMOS transistors in the PUN. Similarly, all the NMOS transistors in the PDN also have the same size. We will also define the NAND2’s “ β ratio” as the ratio between the width of the PMOS transistors and the NMOS transistors – i.e., β = W p /W n . In this problem we will explore how changing β impacts various design metrics by using HSPICE. You should make the

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## This note was uploaded on 01/11/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at Berkeley.

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EE141_HW3_sol - UNIVERSITY OF CALIFORNIA BERKELEY College...

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