EE141_HW4

# EE141_HW4 - UNIVERSITY OF CALIFORNIA BERKELEY College of...

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UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #4 EECS141 Due Thursday, September 24, 5pm, box in 240 Cory PROBLEM 1: Inverter Chain In this problem you will optimize the delay of a chain of four inverters. The load capacitance is C L =64*C in , where C in represent the capacitance of the first inverter in the chain. Assume that the input capacitance of the first inverter is C unit , γ =0.8, and t inv is the unit delay of an inverter as defined in lecture ( i.e., t p = t inv ( γ +f) ). a) Size the inverters (with respect to C in ) to minimize the delay. b) What is the optimal delay? c) Now add an additional, fixed capacitive load of 500*C in after the 3 rd inverter in the chain. With the same sizing as in part a), now what is the delay of the chain? d) [BONUS] How could you modify design of the chain (i.e., change sizes, add or remove stages, etc.) to improve the delay of the circuit from part c)? PROBLEM 2: Complex Logic and LE

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## This note was uploaded on 01/11/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at Berkeley.

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EE141_HW4 - UNIVERSITY OF CALIFORNIA BERKELEY College of...

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