EE141_HW4_sol - UNIVERSITY OF CALIFORNIA, BERKELEY College...

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UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #4 - Solutions EECS141 Due Thursday, September 24, 5pm, box in 240 Cory PROBLEM 1: Inverter Chain In this problem you will optimize the delay of a chain of four inverters. The load capacitance is C L =64*C in , where C in represent the capacitance of the first inverter in the chain. Assume that the input capacitance of the first inverter is C unit , γ =0.8, and t inv is the unit delay of an inverter as defined in lecture ( i.e., t p = t inv ( γ +f) ). a) Size the inverters (with respect to C in ) to minimize the delay. Solution: From the lectures we know that the optimal way to size the inverter chain for minimal delay is to size every inverter for the same fanout f . Since we are given the input and the output capacitance and the number of stages, we can find the total fanout (F) and the fanout of each stage ( f ) as: F = 64 C in C in = 64 f = 64 4 = 22 2.82. Now we know that the optimal sizing for the chain is (starting from the beginning of the chain): C in , fC in , f 2 C in , f 3 C in . The exact numbers are shown on figure below.
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b) What is the optimal delay? Solution: Every stage has the same fanout and therefore the same delay: t d ,1 = t inv ( γ + f ). The total delay is therefore: t d = 4 t d = 4 t inv ( + f ) 14.5 t inv . c) Now add an additional load of 500*C in after the 3 rd inverter in the chain. With the same sizing as in part a), now what is the delay of the chain? Solution: With the sizing from part a), the fanout of the third inverter in the chain will change due to the added capacitive load. The delay of this inverter is now: t d ,3 = t inv ( + f 3 ) = t inv ( + 500 + 22.7 8 ) = t inv ( + 65.3) and therefore the total delay is: t d = 3 t d + t d ,3 = 3 t inv ( + f ) + t inv ( + f 3 ) 77 t inv . d) [BONUS] How could you modify design of the chain (i.e., change sizes, add or remove stages, etc.) to improve the delay of the circuit from part c)? Solution: The large fixed load from this capacitor is now going to be the dominant factor for the overall delay of the chain. This means that we should probably treat the chain of the first 3 inverters as a new sizing problem, still with the same C in for the first stage (and leaving the last inverter the same size), but with the final load equal to 522.7 C in . (We’ll see next week that this heuristic will indeed get us close to the true optimal results.) Assuming we stick with just 3 inverters for this new chain, the new overall fanout will be:
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522.7 522.7 in in C F C == . So, the new f we should be targeting for the first 3 stages is: 3 522.7 8.05 f =≈ Hence, the total delay is now: ,1 ,3 1 3 3 ( ) ( ) 30.2 d d d inv inv inv tt t t f t f t γγ =+ = + + + which is obviously drastically reduced comparing to the result from part c). In fact, we can do even better than this if we allow ourselves to change the number of stages before the fixed capacitive load. In this case, the optimal number of stages is log 4 (522.7) 4.52, which if we round to 4 (5) stages gives an f of 4.78 (3.5) and a delay of ~25.95 t inv (25.11 t inv ).
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This note was uploaded on 01/11/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.

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EE141_HW4_sol - UNIVERSITY OF CALIFORNIA, BERKELEY College...

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