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EE141_HW5

# EE141_HW5 - UNIVERSITY OF CALIFORNIA BERKELEY College of...

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UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #5 EECS141 PROBLEM 1: Logical Effort For this problem, you should assume that C G = 2fF/μm and that the transistors are long- channel for the purpose of calculating LE. a) What is the total path effort from In to Out? b) To minimize the delay, what should the EF/stage for this chain of gates be? c) Size the gates in this chain to minimize the delay from In to Out. Only calculate the input capacitance of the gates; don’t bother to provide the actual transistor sizes. d) Using this sizing, what is the delay (in units of t inv ) of your chain from In rising to Out rising? You can assume that the critical input of the complex gates is always at the “top” of the transistor stacks (i.e., the critical input is always closest to the output node), and that C D /C G = γ = 0.5. e) You present your design to your boss and she tells you that the delay of your circuit is below the specification for the block. She also tells you that your team is over budget on die area. Revise your design such that you save the maximum

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