EE141_HW6 - UNIVERSITY OF CALIFORNIA, BERKELEY College of...

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UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #6 EECS141 Due Thursday, Oct. 15 @ 240 Cory Unless otherwise noted, you should assume the following parameters for all of the problems in this homework: NMOS: L=100nm, V Tn = 0.25V, μ n = 350 cm 2 /(V·s), C ox = 0.95 μ F/cm 2 , v sat = 1e7 cm/s, λ = 0 PMOS: L=100nm, | V Tp | = 0.25V, μ p = 175 cm 2 /(V·s), C ox = 0.65 μ F/cm 2 , v sat = 1e7 cm/s, λ = 0 PROBLEM 1: RC Model Extraction In this problem, you will use the built-in optimization tool in HSPICE to do device characterization. The discussion sessions will cover the syntax needed to perform optimizations in HSPICE, so be sure to attend if you have not used this HSPICE feature before. a) Using the calibration procedure described in the lecture (i.e. Lecture #11 page 21-23), find the linear drain capacitance per μm of width for an NMOS transistor with 100nm channel length. Repeat for a PMOS transistor with 100nm channel length. b)
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This note was uploaded on 01/11/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.

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EE141_HW6 - UNIVERSITY OF CALIFORNIA, BERKELEY College of...

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