EE141_HW6_sol

# EE141_HW6_sol - UNIVERSITY OF CALIFORNIA BERKELEY College...

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UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #6 EECS141 Due Thursday, Oct. 15 @ 240 Cory Unless otherwise noted, you should assume the following parameters for all of the problems in this homework: NMOS: L=100nm, V Tn = 0.25V, μ n = 350 cm 2 /(V·s), C ox = 0.95 μ F/cm 2 , v sat = 1e7 cm/s, λ = 0 PMOS: L=100nm, | V Tp | = 0.25V, μ p = 175 cm 2 /(V·s), C ox = 0.65 μ F/cm 2 , v sat = 1e7 cm/s, λ = 0 PROBLEM 1: RC Model Extraction In this problem, you will use the built-in optimization tool in HSPICE to do device characterization. The discussion sessions will cover the syntax needed to perform optimizations in HSPICE, so be sure to attend if you have not used this HSPICE feature before. a) Using the calibration procedure described in the lecture (i.e. Lecture #11 page 21-23), find the linear drain capacitance per μm of width for an NMOS transistor with 100nm channel length. Repeat for a PMOS transistor with 100nm channel length. Solution: We can use the following setup for NMOS drain capacitance extraction: The NMOS drain capacitance that matches the average delay is ~0.7617fF/ μ m. Similarly, we can extract the drain capacitance for PMOS as shown on the next page:

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The PMOS drain capacitance that matches the average delay is ~0.7776 fF/ μ m. SPICE DECK: * EE141 HW6 P1 a) .LIB '/home/ff/ee141/MODELS/gpdk090_mos.sp' TT_s1v .PARAM Cpermicron=optrange(2f, 0.5f, 5f) *Drain capacitance per micron width .MODEL optmod opt itropt=50 *-------Inverter SUBCKT definition----------- .SUBCKT inv vh vl in out M0 out in vh vh gpdk090_pmos1v L=100n W=2u M1 out in vl vl gpdk090_nmos1v L=100n W=1u .ENDS * Voltage source VDD vdd 0 1.2 * Input Stimulus Vin in 0 PULSE 0 1.2 1ps 10ps 10ps 1ns 2ns * Inverter Chain for calibration X1c vdd 0 in out1c inv M=1 X2c vdd 0 out1c out2c inv M=4 Cc out2c 0 'Cpermicron*48' * Equivalent linear cap * Inverter Chain with MOS drain as load X1t vdd 0 in out1t inv M=1 X2t vdd 0 out1t out2t inv M=4 MdutN out2t gnd gnd gnd gpdk090_nmos1v L=100n W=1u M=48 *MdutP out2t vdd vdd vdd gpdk090_pmos1v L=100n W=1u M=48 * Measure the calibration chain .MEASURE TRAN CALtpLH TRIG v(out1c) VAL=0.6 FALL=2 TARG v(out2c) VAL=0.6 RISE=2 .MEASURE TRAN CALtpHL TRIG v(out1c) VAL=0.6 RISE=2 TARG v(out2c) VAL=0.6 FALL=2 * Measure the chain with transitor drain as load .MEASURE TRAN tpLH TRIG v(out1t) VAL=0.6 FALL=2 TARG v(out2t) VAL=0.6 RISE=2 .MEASURE TRAN tpHL TRIG v(out1t) VAL=0.6 RISE=2 TARG v(out2t) VAL=0.6 FALL=2
* Optimization GOAL .MEASURE errorR PARAM='abs(tpHL-CALtpHL)' GOAL=0 .MEASURE errorF PARAM='abs(tpLH-CALtpLH)' GOAL=0 .OPTIONS accurate .TRAN 0.01p 5n SWEEP OPTIMIZE=optrange RESULTS=errorR,errorF MODEL=optmod .MEASURE Cdpermicro param='Cpermicron' .END b) Now instead of finding the linear drain capacitance for the same NMOS transistor that best matches the delay, find the linear drain capacitance per μm that best matches the power drawn from the inverter supply. Repeat this for a PMOS transistor.

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EE141_HW6_sol - UNIVERSITY OF CALIFORNIA BERKELEY College...

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