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EE141_HW7

# EE141_HW7 - UNIVERSITY OF CALIFORNIA BERKELEY College of...

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UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #7 EECS141 Due Thursday, October 22, 5pm, box in 240 Cory PROBLEM 1: Complex CMOS Gates For this problem you should use the following parameters for the transistors. NMOS: L=100nm, V Tn = 0.25V, n = 350 cm 2 /(V·s), C ox = 0.95 F/cm 2 , v sat = 1e7 cm/s, λ = 0 PMOS: L=100nm, | V Tp | = 0.25V, p = 175 cm 2 /(V·s), C ox = 0.65 F/cm 2 , v sat = 1e7 cm/s, λ = 0 a) Implement the function F = A ( B + C ) + D E . Assuming long-channel transistors, size the devices so that the worst-case drive resistance is the same as an inverter with W N /L =2 and W P /L =4. b) Imagine that input "B" to the gate was always the last one to arrive, making the delay of the gate from B rising or falling to the output falling or rising critical. Please re- arrange the implementation of your gate so that the delay of the gate from B transitioning is minimized. c) Draw a stick diagram of the gate you designed for part b) - you should minimize the diffusion breaks and use a single piece of poly for each input.

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