EE141_HW7 - UNIVERSITY OF CALIFORNIA, BERKELEY College of...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #7 EECS141 Due Thursday, October 22, 5pm, box in 240 Cory PROBLEM 1: Complex CMOS Gates For this problem you should use the following parameters for the transistors. NMOS: L=100nm, V Tn = 0.25V, ! n = 350 cm 2 /(V·s), C ox = 0.95 ! F/cm 2 , v sat = 1e7 cm/s, λ = 0 PMOS: L=100nm, | V Tp | = 0.25V, ! p = 175 cm 2 /(V·s), C ox = 0.65 ! F/cm 2 , v sat = 1e7 cm/s, λ = 0 a) Implement the function F = A ( B + C ) + D E . Assuming long-channel transistors, size the devices so that the worst-case drive resistance is the same as an inverter with W N /L =2 and W P /L =4. b) Imagine that input "B" to the gate was always the last one to arrive, making the delay of the gate from B rising or falling to the output falling or rising critical. Please re- arrange the implementation of your gate so that the delay of the gate from B transitioning is minimized. c) Draw a stick diagram of the gate you designed for part b) - you should minimize the
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 01/11/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at University of California, Berkeley.

Page1 / 3

EE141_HW7 - UNIVERSITY OF CALIFORNIA, BERKELEY College of...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online