UNIVERSITY OF CALIFORNIA, BERKELEY
College of Engineering
Department of Electrical Engineering and Computer Sciences
Elad Alon
Homework #7  Solutions
EECS141
Due Thursday, October 22, 5pm, box in 240 Cory
PROBLEM 1: Complex CMOS Gates
For this problem you should use the following parameters for the transistors.
NMOS:
L=100nm,
V
Tn
= 0.25V,
µ
n
= 350 cm
2
/(V·s), C
ox
= 0.95
µ
F/cm
2
,
v
sat
= 1e7 cm/s,
λ
= 0
PMOS:
L=100nm, 
V
Tp
 = 0.25V,
µ
p
= 175 cm
2
/(V·s), C
ox
= 0.65
µ
F/cm
2
,
v
sat
= 1e7 cm/s,
λ
= 0
a) Implement the function
F
=
A
(
B
+
C
)
+
D
E
.
Assuming longchannel transistors, size the
devices so that the worstcase drive resistance is the same as an inverter with W
N
/L =2
and W
P
/L =4.
Solution:
b) Imagine that input "B" to the gate was always the last one to arrive, making the delay
of the gate from B rising or falling to the output falling or rising critical. Please re
arrange the implementation of your gate so that the delay of the gate from B transitioning
is minimized.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Solution:
In order to minimize the delay from input B to Out, the least amount of parasitic caps
should be charged/discharged. This happens when the transistors connected to input B are
the closest to the output (i.e., at the top of the stack). The revised gate
is shown below:
c) Draw a stick diagram of the gate you designed for part b)  you should minimize the
diffusion breaks and use a single piece of poly for each input.
Solution:
In order to implement the gate without any diffusion breaks, we need to find a Consistent
Euler path for both the pullup and the pulldown network. Based on the logic graph
shown below, one such path is D E A B C (note that there are other consistent Euler paths
as well – any correct solution will receive full credit).
d) Now resize the gate to match the worstcase pullup and pulldown resistances using
the velocity saturated model. What is the LE from the B input?
Solution:
Since we’re interested in logical effort, the first thing we need to do is figure out to size
the reference inverter – i.e., what ratio between NMOS and PMOS widths provides equal
pulldown and pullup currents.
Setting the two currents equal to each other:
I
D
,1
xN
=
W
N
⋅
C
ox
,
N
v
sat
(
V
gs
−
V
th
)
2
(
V
gs
−
V
th
)
+
ε
c
,
N
L
=
W
P
C
ox
,
P
v
sat
(
V
gs
−
V
th
)
2
(
V
gs
−
V
th
)
+
ε
c
,
P
L
=
I
D
,1
xP
we get that
W
P
/
W
N
≈
2
, meaning that we can continue using the reference inverter from
part a) for this part of the problem as well.
Now, in order to size the gate itself we need to equate the current through a stack of three
NMOS transistors to that of the single NMOS device inside of the reference inverter.
In
order to do this we need to realize that a stack of N transistors is equivalent to a single
transistor with N times the length, as shown in the example below:
Therefore, for the pulldown side we get:
I
D
,1
xN
=
0.2
µ
m
⋅
C
ox
,
N
v
sat
(
V
gs
−
V
th
)
2
(
V
gs
−
V
th
)
+
ε
c
,
N
L
=
W
N
C
ox
,
N
v
sat
(
V
gs
−
V
th
)
2
(
V
gs
−
V
th
)
+
ε
c
,
N
3
L
=
I
D
,3
xN
,
where
ε
c
,
N
L
=
2
v
sat
µ
n
L
=
0.57
V
and hence
W
N
=
0.35
µ
m
.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
This is the end of the preview.
Sign up
to
access the rest of the document.
 Spring '08
 Staff
 Gate, Christo and JeanneClaude, gpdk090_nmos1v W=wN L=length, gnd gpdk090_nmos1v W=wN

Click to edit the document details