EE141_HW8

# EE141_HW8 - C L = 300fF, C in = 5fF, C G = 2fF/μm, C D =...

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UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #8 EECS141 Due Tuesday, Nov. 24 th @ 240 Cory PROBLEM 1: DOMINO LOGIC AND CHARGE SHARING a) Implement the logic shown below as a single complex, dynamic gate (with four inputs) followed by an inverter. A B D X C b) What pattern of the inputs P 1 , G 0 , and G 1 results in the worst-case drop in voltage on node G 1:0 _b due to charge sharing for the gate shown below? Assuming V DD = 1.2V, C G = 2fF/μm, and C D = 1.5fF/μm, what is this worst-case voltage? PROBLEM 2: DOMINO SIZING AND DELAY Consider the domino circuit shown on the next page. Assume long-channel transistors,

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Unformatted text preview: C L = 300fF, C in = 5fF, C G = 2fF/μm, C D = 1.5fF/μm, and that input signal C is the last one to arrive. a) Find the logical effort of each stage in the critical path for the evaluation edge (rising edge of Out). b) Find WN1 and WN2 to give minimal delay. c) Estimate the delay of the critical path in F04. Include the worst-case parasitic delay terms. Recall that 1FO4 is equal to (4+ γ )t inv . d) From the standpoint of minimum delay, is this the optimum number of stages? If not, how many stages would you use to minimize the delay? CLK CLK C D V DD V DD W N1 W N1 W N1 2/3*W N1 W N2 4W N2 Out A B W N1 W N1 C L...
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## This note was uploaded on 01/11/2011 for the course EE 141 taught by Professor Staff during the Spring '08 term at Berkeley.

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EE141_HW8 - C L = 300fF, C in = 5fF, C G = 2fF/μm, C D =...

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